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5962-8946302XC: 产品描述Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小1MB，共43页; 制造商Atmel (Microchip)

下载文档详细参数选型对比全文预览文档解析

5962-8946302XC概述

Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68

5962-8946302XC规格参数

参数名称	属性值
是否Rohs认证	不符合
零件包装代码	PGA
包装说明	PGA, PGA68,10X10
针数	68
Reach Compliance Code	unknown
ECCN代码	3A001.A.2.C
JESD-30 代码	S-CPGA-P68
JESD-609代码	e4
长度	26.92 mm
端子数量	68
最高工作温度	125 °C
最低工作温度	-55 °C
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	PGA
封装等效代码	PGA68,10X10
封装形状	SQUARE
封装形式	GRID ARRAY
电源	5 V
认证状态	Not Qualified
筛选级别	MIL-STD-883
座面最大高度	4.82 mm
最大压摆率	150 mA
最大供电电压	5.5 V
最小供电电压	4.5 V
标称供电电压	5 V
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子面层	Gold (Au)
端子形式	PIN/PEG
端子节距	2.54 mm
端子位置	PERPENDICULAR
宽度	26.92 mm
uPs/uCs/外围集成电路类型	MATH PROCESSOR, COPROCESSOR
Base Number Matches	1

文档解析

TS68882是一款高性能的浮点协处理器，设计用于与THOMSON TS68000系列微处理器家族配合使用，特别是作为TS68020/68030 32位微处理器单元（MPU）的协处理器。要利用TS68882协处理器的算术单元进行高效的数学运算，可以遵循以下几个关键点：

理解协处理器架构：TS68882拥有8个通用浮点数据寄存器，每个寄存器支持80位的扩展精度实数数据格式，包括64位尾数、1位符号位和15位的有符号指数。此外，它还拥有一个67位的算术单元，用于快速计算，并且具有高于扩展精度格式的中间精度。
使用专用硬件：TS68882具有专门硬件用于高速转换单精度、双精度和扩展格式数据以及内部扩展格式。
指令集扩展：TS68882的指令集是TS68000系列的自然扩展，包括35个算术操作，支持所有TS68000系列的寻址模式。
并发指令执行：TS68882能够与主处理器完全并发执行指令，这意味着可以同时执行多个浮点指令，提高计算效率。
遵循IEEE 754标准：TS68882完全符合IEEE 754标准，包括所有要求和建议，这确保了运算的准确性和一致性。
支持额外的数学函数：除了IEEE标准定义的函数外，TS68882还支持一系列三角函数和超越函数。
数据类型多样性：TS68882支持多种数据类型，包括字节、字和长整数；单精度、双精度和扩展精度实数；以及打包的二进制编码的十进制字符串实数。
利用内部常数：TS68882在片上ROM中提供了22个常数，包括π、e和10的幂，这些可以直接在计算中使用，而无需额外的存储或计算开销。
虚拟内存/机器操作：TS68882支持虚拟内存/机器操作，这可以提高内存管理的效率。
中断和上下文切换：TS68882具备高效的机制来处理程序调用、上下文切换和中断处理。
与主处理器的通信：通过独立的状态机控制主处理器通信，实现流水线指令处理。
配置和兼容性：TS68882可以使用任何宿主处理器，在8位、16位或32位数据总线上工作，并在不同的时钟频率下运行，从16.67 MHz到33 MHz不等。

通过以上方式，可以充分利用TS68882协处理器的算术单元来进行高效的数学运算。开发者需要熟悉TS68882的指令集和编程模型，以便编写能够最大化协处理器性能的程序。

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Features

•

Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit

•

Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit

Signed Exponent)

A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision

Greater than the Extended Precision Format

A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)

Special-purpose Hardware for High-speed Conversion Between Single, Double, and

Extended Formats and the Internal Extended Format

An Independent State Machine to Control Main Processor Communication for

Pipelined Instruction Processing

Forty-six Instructions, Including 35 Arithmetic Operations

Full Conformation to the IEEE 754 Standard, Including All Requirements and

Suggestions

Support of Functions Not Defined by the IEEE Standard, Including a Full Set of

Trigonometric and Transcendental Functions

Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended

Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers

Twenty-two Constants Available In The On-chip ROM, Including

π,

e, and Powers of 10

Virtual Memory/Machine Operations

Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling

Fully Concurrent Instruction Execution with the Main Processor

Fully Concurrent Instruction Execution of Multiple Floating-point Instructions

Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus

Available in 16.67, 20, 25 and 33 MHz for T

from -55°C to +125°C

= 5V

10%

CMOS

Enhanced

Floating-point

Co-processor

TS68882

Description

The TS68882 enhanced floating-point co-processor is a full implementation of the

IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON

TS68000 Family of microprocessors. It is a pin and software compatible upgrade of

the TS68881 with optimized MPU interface that provides over 1.5 times the perfor-

mance of the TS68881. It is implemented using VLSI technology to give systems

designers the highest possible functionality in a physically small device.

Intended primarily for use as a co-processor to the TS68020/68030 32-bit micropro-

cessor units (MPUs), the TS68882 provides a logical extension to the main MPU

integer data processing capabilities. It does this by providing a very high performance

floating-point arithmetic unit and a set of floating-point data registers that are utilized

in a manner that is analogous to the use of the integer data registers. The TS68882

instruction set is a natural extension of all earlier members of the TS68000 Family, and

supports all of the addressing modes of the host MPU. Due to the flexible bus inter-

face of the TS68000 Family, the TS68882 can be used with any of the MPU devices of

the TS68000 Family, and it may also be used as a peripheral to non-TS68000

processors.

Screening/Quality

This product could be manufactured

in full compliance with either:

•

MIL-STD-883 Class B

DESC 5962-89436

or According to ATMEL-

Grenoble Standards

Rev. 2119A–HIREL–04/02

R suffix

PGA 68

Ceramic Pin Grid Array

F suffix

CQFP 68

Ceramic Quad Flat Pack

Introduction

The TS68882 is a high-performance floating-point device designed to interface with the

TS68020 or TS68030 as a co-processor. This device fully supports the TS68000 virtual

machine architecture, and is implemented in HCMOS, Atmel’s low power, small geome-

try process. This process allows CMOS and HMOS (high-density NMOS) gates to be

combined on the same device. CMOS structures are used where speed and low power

is required, and HMOS structures are used where minimum silicon area is desired. The

HCMOS technology enables the TS68882 to be very fast while consuming less power

than comparable HMOS, and still have a reasonably small die size.

With some performance degradation, the TS68882 can also be used as a peripheral

processor in systems where the TS68020 or TS68030 is not the main processor (i.e.,

TS68000, TS68010). The configuration of the TS68882 as a peripheral processor or co-

processor may be completely transparent to user software (i.e., the same object code

may be executed in either configuration).

The architecture of the TS68882 appears to the user as a logical extension of the

TS68000 Family architecture. Coupling of the co-processor interface allows the

TS68020/TS68030 programmer to view the TS68882 registers as though the registers

are resident in the TS68020/TS68030. Thus, a TS68020 or TS68030/TS68882 device

pair appears to be one processor that supports seven floating-point and integer data

types, and has eight integer data registers, eight address registers, and eight floating-

point data registers.

As shown in Figure 1, the TS68882 is internally divided into four processing elements;

the Bus Interface Unit (BIU), the Conversion Control Unit (CCU), the Execution Control

Unit (ECU), and the Microcode Control Unit (MCU). The BIU communicates with the

main processor, the CCU controls the main processor communications dialog and per-

forms some data conversions, and the ECU and MCU execute most floating-point

calculations.

The BIU contains the co-processor interface registers, and the 32-bit control, and

instruction address registers. In addition to these registers, the register select and

DSACK timing control logic is contained in the BIU. Finally, the status flags used to mon-

itor the status of communications with the main processor are contained in the BIU.

The CCU contains special-purpose hardware that performs conversions between the

single, double, and extended precision memory data formula and the internal data for-

mat used by the ECU. It also contains a state machine that controls communications

with the main processor during co-processor interface dialogs.

The eight 80-bit floating-point data registers (FP0-FP7) are located in the ECU. In addi-

tion to these registers, the ECU contains a high-speed 67-bit arithmetic unit used for

both mantissa and exponent calculations, a barrel shifter that can shift from 1-bit to 67-

bits in one machine cycle, and ROM constants (for use by the internal algorithms or user

programs).

The MCU contains the clock generator, a two-level microcoded sequencer that controls

the ECU, the microcode ROM, and self-test circuitry. The built-in self-test capabilities of

the TS68882 enhance reliability and ease manufacturing requirements; however, these

diagnostic functions are not available to the user.

TS68882

2119A–HIREL–04/02

5962-8946302XC相似产品对比

	5962-8946302XC	5962-8946304XC	5962-8946303YC	5962-8946302YC	5962-8946302YA	5962-8946301YC	5962-8946302XA	5962-8946301XC	5962-8946303XC
描述	Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68	Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68	Math Coprocessor, CMOS, CQFP68, CERAMIC, QFP-68	Math Coprocessor, CMOS, CQFP68, CERAMIC, QFP-68	Math Coprocessor, CMOS, CQFP68, CERAMIC, QFP-68	Math Coprocessor, CMOS, CQFP68, CERAMIC, QFP-68	Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68	Math Coprocessor, 32-Bit, CMOS, CPGA68, CERAMIC, PGA-68	Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	PGA	PGA	QFP	QFP	QFP	QFP	PGA	PGA	PGA
包装说明	PGA, PGA68,10X10	PGA, PGA68,10X10	QFP, QFP68,1.1SQ,50	QFP, QFP68,1.1SQ,50	QFP, QFP68,1.1SQ,50	QFP, QFP68,1.1SQ,50	PGA, PGA68,10X10	PGA, PGA68,10X10	PGA, PGA68,10X10
针数	68	68	68	68	68	68	68	68	68
Reach Compliance Code	unknown	unknown	unknown	unknown	compliant	unknown	compliant	unknown	unknown
ECCN代码	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
JESD-30 代码	S-CPGA-P68	S-CPGA-P68	S-CQFP-G68	S-CQFP-G68	S-CQFP-G68	S-CQFP-G68	S-CPGA-P68	S-CPGA-P68	S-CPGA-P68
JESD-609代码	e4	e4	e4	e4	e0	e4	e0	e4	e4
长度	26.92 mm	26.92 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	26.92 mm	26.92 mm	26.92 mm
端子数量	68	68	68	68	68	68	68	68	68
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	PGA	PGA	QFP	QFP	QFP	QFP	PGA	PGA	PGA
封装等效代码	PGA68,10X10	PGA68,10X10	QFP68,1.1SQ,50	QFP68,1.1SQ,50	QFP68,1.1SQ,50	QFP68,1.1SQ,50	PGA68,10X10	PGA68,10X10	PGA68,10X10
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	FLATPACK	FLATPACK	FLATPACK	FLATPACK	GRID ARRAY	GRID ARRAY	GRID ARRAY
电源	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
筛选级别	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883
座面最大高度	4.82 mm	4.82 mm	3.43 mm	3.43 mm	3.43 mm	3.43 mm	4.184 mm	4.82 mm	4.82 mm
最大压摆率	150 mA	150 mA	150 mA	150 mA	150 mA	150 mA	150 mA	150 mA	150 mA
最大供电电压	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	NO	YES	YES	YES	YES	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子面层	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Tin/Lead (Sn/Pb) - hot dipped	Gold (Au)	Tin/Lead (Sn/Pb) - hot dipped	Gold (Au)	Gold (Au)
端子形式	PIN/PEG	PIN/PEG	GULL WING	GULL WING	GULL WING	GULL WING	PIN/PEG	PIN/PEG	PIN/PEG
端子节距	2.54 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm
端子位置	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	QUAD	QUAD	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
宽度	26.92 mm	26.92 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	26.92 mm	26.92 mm	26.92 mm
uPs/uCs/外围集成电路类型	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR	MATH PROCESSOR, COPROCESSOR
Base Number Matches	1	1	1	1	1	1	1	1	1

5962-8946302XC

5962-8946302XC概述

5962-8946302XC规格参数

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5962-8946302XC相似产品对比

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