DATASHEET
LOW EMI CLOCK GENERATOR
Description
The MK5814C device generates a low EMI output clock
from a clock or crystal input. The device is designed to
dither a high emissions clock to lower EMI in consumer
applications. Using IDT’s proprietary mix of analog and
digital Phase Locked Loop (PLL) technology, the device
spreads the frequency spectrum of the output and reduces
the frequency amplitude peaks by several dB. The
MK5814C offers both centered and down spread from a
high-speed clock input. The multiplier is a fixed 4x.
For different multiplier configurations, use the MK5811C
(1x) or MK5812 (2x).
IDT offers many other clocks for computers and computer
peripherals. Consult IDT when you need to remove crystals
and oscillators from your board.
MK5814C
Features
•
•
•
•
•
•
•
•
•
Packaged in 8-pin SOIC
Provides a spread spectrum output clock
Supports printers and flat panel controllers
Accepts a clock or crystal input (provides same
frequency dithered output)
Input frequency range of 4 to 32 MHz with spread off
Input frequency range of 4 to 25 MHz with spread on
4X frequency multiplication
Center spread, down spread, and spread off settings
Peak reduction by 8 dB to 16 dB typical on 3rd through
19th odd harmonics
•
Operating voltage of 3.3 V
•
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
Spread Direction
FRSEL
2
X1/CLK
Clock Buffer/
Crystal
Ocsillator
X2
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
SSCLK
The crystal requires external capacitors
for accurate tuning of the clock
GND
IDT®
LOW EMI CLOCK GENERATOR
1
MK5814C
REV C 070612
MK5814C
LOW EMI CLOCK GENERATOR
SSCG
Pin Assignment
Spread Direction and Spread
Percentage
8
7
6
5
X2
VDD
FRSEL
SSCLK
S1
Pin 3
0
0
0
M
M
M
1
1
1
S0
Pin 4
0
M
1
0
M
1
0
M
1
Spread
Direction
Center
Center
Center
Center
No Spread
Down
Down
Down
Down
Spread
Percentage
±1.4
±1.1
±0.6
±0.5
-
-1.6
-2.0
-0.7
-3.0
X1/ICLK
GND
S1
S0
1
2
3
4
8-pin (150 mil) SOIC
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Frequency Selection
Product
MK5811C
1
FRSEL
(pin 6)
0
1
M
MK5812
1
0
1
M
MK5814C
0
1
M
Input
Freq. Range
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
Multiplier
X1
X1
X1
X2
X2
X2
X4
X4
X4
Output
Freq. Range
4.0 to 8.0 MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
8.0 to 16.0MHz
16.0 to 32.0MHz
32.0 to 64.0MHz
16.0 to 32.0MHz
32.0 to 64.0MHz
64.0 to 128MHz
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Note 1: The information in this datasheet does not apply to
the MK5811C and MK5812 as each have independent
datasheets available at www.idt.com.
IDT®
LOW EMI CLOCK GENERATOR
2
MK5814C
REV C 070612
MK5814C
LOW EMI CLOCK GENERATOR
SSCG
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/ICLK
GND
S1
S0
SSCLK
FRSEL
VDD
X2
Input
Power
Input
Input
Output
Input
Power
XO
Connect to 4-32 MHz crystal or clock input.
Connect to ground.
Function select 1 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Function select 0 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Clock output with Spread spectrum
Function select for input frequency range. Default to mid-level “M”.
Connect to +3.3 V.
Crystal connection to 4-32 MHz crystal. Leave unconnected for clock
External Components
The MK5814C requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, observe the following guidelines:
1) Mount the 0.01µF decoupling capacitor on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to the VDD pin and
the PCB trace to the ground via should be kept as short as
possible.
2) To minimize EMI, place the 33Ω series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through other
signal layers. Other signal traces should be routed away
from the MK5814C device. This includes signal traces
located underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 7 and 2. Connect the
capacitor as close to these pins as possible. For optimum
device performance, mount the decoupling capacitor on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
Use series termination when the PCB trace between the
clock output and the load is over 1 inch. To series terminate
a 50Ω trace (a commonly used trace impedance), place a
33Ω resistor in series with the clock line. Place the resistor
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Tri-level Select Pin Operation
The S1 and S0 select pins are tri-level, meaning that they
have three separate states to make the selections shown in
the table on page 2. To select the M (mid) level, the
connection to these pins must be eliminated by either
floating them originally, or tri-stating the GPIO pins which
drive the select pins.
IDT®
LOW EMI CLOCK GENERATOR
3
MK5814C
REV C 070612
MK5814C
LOW EMI CLOCK GENERATOR
SSCG
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant crystal. To optimize the
initial accuracy, connect crystal capacitors from pins X1 to
ground and X2 to ground. The value of these capacitors is
given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. For
example, a crystal with a 16 pF load capacitance uses two
20 pF [(16-6) x 2] capacitors.
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax)
and minimum frequency of the clock (fmin) determine this
band of frequencies. The time required to transition from
fmin to fmax and back to fmin is the period of the Modulation
Rate. The Modulation Rate of SSCG clocks are generally
referred to in terms of frequency, or
fmod = 1/Tmod
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
The Spread Spectrum modulation Rate, fmod, is given by
the following formula:
fmod = fin/DR
where; fmod is the Modulation Rate, fin is the Input
Frequency and DR is the Divider Ratio as given in the
“Modualtion Rate Divider Ratios” table. Notice that Input
Frequency Range is set by FRSEL
Spread Spectrum Profile
The MK5814C is a low EMI clock generator using a
optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
Modulation R
ate
Frequency
Modulation Rate Divider Ratios
FRSEL
0
Time
Input Freq. Range
4 to 8 MHz
8 to 16 MHz
16 to 32 MHz
Divider Ratio (DR)
128
256
512
1
M
IDT®
LOW EMI CLOCK GENERATOR
4
MK5814C
REV C 070612
MK5814C
LOW EMI CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK5814C. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device, at
these or any other conditions, above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+85
3.63
Units
°
C
V
IDT®
LOW EMI CLOCK GENERATOR
5
MK5814C
REV C 070612
FPGA/CPLD
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