DATA SHEET
1GB Unbuffered DDR2 SDRAM DIMM
EBE11UD8ABFA
(128M words
×
64 bits, 2 Ranks)
Description
The EBE11UD8ABFA is 128M words
×
64 bits, 2 ranks
DDR2 SDRAM unbuffered module, mounting 16 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA
)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
•
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
•
1.8V power supply
•
Data rate: 533Mbps/400Mbps (max.)
•
1.8V (SSTL_18 compatible) I/O
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
•
Four internal banks for concurrent operation
(Component)
•
Data mask (DM) for write data
•
Burst lengths: 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Auto precharge operation for each burst access
•
Auto refresh and self refresh modes
•
7.8µs average periodic refresh interval
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0365E50 (Ver. 5.0)
Date Published August 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2004
EBE11UD8ABFA
Pin Description
Pin name
A0 to A13
A10 (AP)
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
ODT0, ODT1
NC
Function
Address input
Row address
Column address
Auto precharge
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
ODT control
No connection
A0 to A13
A0 to A9
Data Sheet E0365E50 (Ver. 5.0)
4
EBE11UD8ABFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Bit5 Bit4
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
0
Bit3
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
Bit2
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
Bit1 Bit0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Hex value
80H
08H
08H
0EH
0AH
61H
40H
00H
05H
3DH
50H
50H
60H
00H
82H
08H
00H
00H
0CH
04H
38H
00H
02H
00H
30H
3DH
50H
50H
60H
50H
60H
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
10
2
64
0
SSTL 1.8V
3.75ns*
1
5.0ns*
1
0.5ns*
1
0.6ns*
1
None.
7.8µs
×
8
None.
0
4,8
4
3, 4, 5
0
Unbuffered
Normal
VDD ± 0.1V
3.75ns*
1
5.0ns*
1
0.5ns*
1
0.6ns*
1
5.0ns*
1
0.6ns*
1
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = 5
-5C
-4A
SDRAM access from clock (tAC)
-5C
-4A
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
Reserved
DIMM type information
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 4
-5C
-4A
24
Maximum data access time (tAC) from
clock at CL = 4
0
-5C
-4A
0
Minimum clock cycle time at CL = 3
0
-5C, -4A
Maximum data access time (tAC) from
clock at CL = 3
0
-5C, -4A
25
26
Data Sheet E0365E50 (Ver. 5.0)
5
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
