DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AKFA
(64M words
×
72 bits, 1 Rank)
Description
The EBD51RC4AKFA is a 64M words
×
72 bits, 1 rank
Double Data Rate (DDR) SDRAM Module, mounting 18
pieces of DDR SDRAM sealed in TSOP package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2-bit prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
•
2.5V power supply
•
Data rate: 333Mbps/266Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs and outputs are synchronized with DQS
•
4 internal banks for concurrent operation
(Component)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
•
1 piece of PLL clock driver, 2 pieces of register
drivers and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD)
Document No. E0377E20 (Ver. 2.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory,Inc. 2003-2004
EBD51RC4AKFA
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/CS0
CKE0
CK0
/CK0
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
/RESET
NC
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD identification flag
Reset pin (forces register inputs low)
No connection
A0 to A12
A0 to A9, A11
Bank select address
Data Sheet E0377E20 (Ver. 2.0)
4
EBD51RC4AKFA
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
DDR SDRAM cycle time, CL = X
-6B
-7A, -7B
SDRAM access from clock (tAC)
-6B
-7A, -7B
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
Bit3
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
1
0
1
0
0
1
0
0
0
0
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
Hex value
80H
08H
07H
0DH
0BH
01H
48H
00H
04H
60H
75H
70H
75H
02H
82H
04H
04H
01H
0EH
04H
0CH
01H
02H
26H
C0H
75H
A0H
70H
75H
00H
00H
48H
50H
Comments
128
256 byte
SDRAM DDR
13
11
1
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*
3
Voltage interface level of this assembly 0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
10
0.70ns*
3
0.75ns*
3
ECC
7.8 µs
Self refresh
×
4
×
4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*
3
11
12
13
14
15
16
17
18
19
20
21
22
23
Minimum clock cycle time at CLX - 0.5
0
-6B, -7A
-7B
1
Maximum data access time (tAC) from
0
clock at CLX - 0.5
-6B
-7A, -7B
0
0
Minimum clock cycle time at CLX - 1
24
0.70ns*
3
0.75ns*
3
25
26
27
Maximum data access time (tAC) from
0
clock at CLX - 1
Minimum row precharge time (tRP)
0
-6B
-7A, -7B
0
18ns
20ns
Data Sheet E0377E20 (Ver. 2.0)
5
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