CY8CLED04
EZ-Color™ HB LED Controller
Features
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HB LED Controller
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Configurable Dimmers Support up to Four
Independent LED Channels
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8 to 32 Bits of Resolution per Channel
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Dynamic Reconfiguration Enables LED
Controller plus other Features; CapSense, Battery Charging,
and Motor Control
Visual Embedded Design, PSoC Express
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LED Based Express Drivers
• Binning Compensation
• Temperature Feedback
• DMX512
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PrISM Modulation Technology
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Reduces Radiated EMI
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Reduces Low Frequency Blinking
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Advanced Peripherals (PSoC Blocks)
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4 Digital PSoC Blocks Provide:
• 8-to 32-Bit Timers, Counters, and PWMs
• Up to 2 Full-Duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPI/O Pins
❐
Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
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Complex Peripherals by Combining Blocks
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Capacitive Sensing Application Capability
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Complete Development Tools
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Free Development Software
• PSoC Designer™
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Full Featured, In-Circuit Emulator and
Programmer
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Full Speed Emulation
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Complex Breakpoint Structure
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128 KBytes Trace Memory
Programmable Pin Configurations
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25 mA Sink on all GPI/O
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Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
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Up to 12 Analog Inputs on GPI/O
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Four 30 mA Analog Outputs on GPI/O
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Configurable Interrupt on all GPI/O
Flexible On-Chip Memory
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16K Flash Program Storage 50,000 Erase/Write Cycles
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1K SRAM Data Storage
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In-System Serial Programming (ISSP)
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Partial Flash Updates
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Flexible Protection Modes
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EEPROM Emulation in Flash
Full Speed USB (12 Mbps)
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Four Uni-Directional Endpoints
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One Bi-Directional Control Endpoint
❐
USB 2.0 Compliant
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Dedicated 256 Byte Buffer
❐
No External Crystal Required
Cypress Semiconductor Corporation
Document Number: 001-13108 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 10, 2009
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CY8CLED04
Logic Block Diagram
Port 7
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
Sleep and
Watchdog
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM
CPU Core (M8C)
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Digital
2
Decimator
Clocks MACs
Type 2
I2C
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Document Number: 001-13108 Rev. *A
Page 2 of 36
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CY8CLED04
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for high brightness LED applications requiring intelligent
dimming control. EZ-Color devices combine the power and flexi-
bility of PSoC (Programmable System-on-Chip™); with
Cypress's PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family support up to 16 independent LED channels
with up to 32 bits of resolution per channel, enabling lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify implemen-
tation of fixed color points through temperature and LED binning
compensation. EZ-Color's virtually limitless analog and digital
customization enable simple integration of features in addition to
intelligent lighting, such as CapSense, battery charging, image
stabilization, and motor control during the development process.
These features, along with Cypress's best-in-class quality and
design support, make EZ-Color the ideal choice for intelligent HB
LED control applications.
selected from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit periph-
erals, which are called user module references.
Digital peripheral configurations include:
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PrISM (8 to 32 bit)
Full speed USB (12 Mbps)
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 24 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8-bit with selectable parity
SPI master and slave
I2C slave and multi-master
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA
Generators (8 to 32 bit)
Target Applications
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LCD Backlight
Large Signs
General Lighting
Architectural Lighting
Camera/Cell Phone Flash
Flashlights
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPI/O (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
68 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The EZ-Color family incorporates flexible internal clock gener-
ators, including a 24 MHz IMO (internal main oscillator) accurate
to 8 percent over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. The clocks, together with program-
mable clock dividers (as a System Resource), provide the flexi-
bility to integrate almost any timing requirement into the EZ-Color
device. In USB systems, the IMO self-tunes to ± 0.25% accuracy
for USB communication.
EZ-Color GPI/Os provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
The digital blocks can be connected to any GPI/O through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Charac-
teristics.
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 001-13108 Rev. *A
Page 3 of 36
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CY8CLED04
The Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
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Figure 2. Analog System Block Diagram
All IO
(Except Port 7)
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
Analog
Mux Bus
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
Filters (2 and 4 pole band-pass, low-pass, and notch)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (up to 2, with 16 selectable thresholds)
DACs (up to 2, with 6- to 9-bit resolution)
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
1.3V reference (as a System Resource)
DTMF Dialer
Modulators
Correlators
Peak Detectors
Many other topologies possible
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Block
Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-13108 Rev. *A
Page 4 of 36
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CY8CLED04
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins can be connected to the bus individually or in any combi-
nation. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It can be split
into two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
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Additional System Resources
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state-
ments describing the merits of each resource follow.
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Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math as well
as digital filters.
Decimator provides a custom hardware filter for digital signal
processing apps. including creation of Delta Sigma ADCs.
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Versatile analog multiplexer system.
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Track pad, finger sensing.
Chip-wide mux that allows analog input from up to 48 I/O pins.
Crosspoint connection between any I/O pin combinations.
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When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under
http://www.cypress.com
>
DESIGN RESOURCES > Application Notes. In general, and
unless otherwise noted in the relevant Application Notes, the
minimum signal-to-noise ratio (SNR) for CapSense applications
is 5:1.
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EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Table 1. EZ-Color Device Characteristics
PSoC Part
Number
CY8CLED04
CY8CLED08
CY8CLED16
CapSense
Yes
No
No
Page 5 of 36
LED
Channels
Analog
Columns
Analog
Outputs
Analog
Inputs
Analog
Blocks
Digital
Blocks
Digital
I/O
Digital
Rows
SRAM
Size
1K
256 Bytes
2K
Flash
Size
16K
16K
32K
4
8
16
56
44
64
1
2
4
4
8
16
48
12
12
2
4
4
2
4
4
6
12
12
Document Number: 001-13108 Rev. *A
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