CAT28F001
1 Megabit CMOS Boot Block Flash Memory
FEATURES
s
Fast Read Access Time: 70/90/120/150 ns
s
On-Chip Address and Data Latches
s
Blocked Architecture
Licensed Intel
second source
s
Deep Powerdown Mode
s
s
s
s
s
— One 8 KB Boot Block w/ Lock Out
• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
Low Power CMOS Operation
12.0V
±
5% Programming and Erase Voltage
Automated Program & Erase Algorithms
High Speed Programming
Commercial, Industrial and Automotive
Temperature Ranges
s
s
s
s
s
— 0.05
µ
A I
CC
Typical
— 0.8
µ
A I
PP
Typical
Hardware Data Protection
Electronic Signature
100,000 Program/Erase Cycles and 10 Year
Data Retention
JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
Reset/Deep Power Down Mode
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
ADDRESS
COUNTER
I/O BUFFERS
WRITE STATE
MACHINE
RP
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
COMPARATOR
ERASE VOLTAGE
SWITCH
STATUS
REGISTER
SENSE
AMP
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
28F001 F01
A0–A16
VOLTAGE VERIFY
SWITCH
X-DECODER
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25071-00 2/98 F-1
1
CAT28F001
PIN CONFIGURATION
DIP Package (P)
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
RP
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Package (N)
VCC
WE
RP
29
28
27
26
25
24
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
A12
A15
A16
VPP
4 3 2 1 32 31 30
A14
A13
A8
A9
A11
OE
11
23
A10
12
22
F02
CE
28F001
13
21
I/O7
14 15 16 17 18 19 20
I/O1
I/O2
VSS
I/O3
TSOP Package (Standard Pinout) (T)
A11
A9
A8
A13
A14
RP
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN FUNCTIONS
Pin Name
A
0
–A
16
I/O
0
–I/O
7
CE
OE
WE
V
CC
V
SS
V
PP
RP
Input
Type
Input
I/O
Input
Input
Input
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
Power Down
I/O4
I/O5
I/O6
28F001 F03
Doc. No. 25071-00 2/98 F-1
2
CAT28F001
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
(Except A
9
,
RP, OE,
V
CC
and V
PP
)
Voltage on Pin A
9
,
RP
AND
OE
with
Respect to Ground
(1)
................... –2.0V to +13.5V
V
PP
with Respect to Ground
during Program/Erase
(1)
.............. –2.0V to +14.0V
V
CC
with Respect to Ground
(1)
............ –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz
Limits
Symbol
C
IN(3)
C
OUT(3)
C
VPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
V
PP
Supply Capacitance
Min
Max.
8
12
25
Units
pF
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
V
PP
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
3
Doc. No. 25071-00 2/98 F-1
CAT28F001
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V
±10%,
unless otherwise specified
Limits
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
PPD
I
CC1
I
CC2(1)
I
CC3(1)
I
PPS
I
PP1
I
PP2(1)
I
PP3(1)
V
IL
V
OL
V
IH
V
OH
V
ID
I
ID
I
CCD
I
CCES
I
PPES
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
PP
Deep Powerdown Current
V
CC
Active Read Current
V
CC
Programming Current
V
CC
Erase Current
V
PP
Standby Current
V
PP
Read Current
V
PP
Programming Current
V
PP
Erase Current
Input Low Level
Output Low Level
Input High Level
Output High Level
A
9
Signature Voltage
A
9
Signature Current
V
CC
Deep Powerdown Current
V
CC
Erase Suspend Current
V
PP
Erase Suspend Current
2.0
2.4
11.5
13.0
500
1.0
10
300
–0.5
Min.
Max.
±1.0
±10
100
1.5
1.0
30
20
20
±10
200
200
30
30
0.8
0.45
V
CC
+0.5
Unit
µA
µA
µA
mA
µA
mA
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
µA
µA
mA
µA
I
OH
= 2.5mA, V
CC
= 4.5V
A
9
= V
ID
A
9
= V
ID
RP = GND±0.2V
Erase Suspended CE = V
IH
Erase Suspended V
PP
=V
PPH
I
OL
= 5.8mA, V
CC
= 4.5V
Test Conditions
V
IN
= V
CC
or V
SS
V
CC
= 5.5V
V
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V
CE = V
CC
±0.2V
= RP
V
CC
= 5.5V
CE = RP = V
IH
, V
CC
= 5.5V
RP = GND±0.2V
V
CC
= 5.5V, CE = V
IL
,
I
OUT
= 0mA, f = 8 MHz
V
CC
= 5.5V,
Programming in Progress
V
CC
= 5.5V,
Erase in Progress
V
PP
<
V
CC
V
PP
>
V
CC
V
PP
= V
PPH
V
PP
= V
PPH
,
Programming in Progress
V
PP
= V
PPH
,
Erase in Progress
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25071-00 2/98 F-1
4
CAT28F001
SUPPLY CHARACTERISTICS
Limits
Symbol
V
LKO
V
CC
V
PPL
V
PPH
V
HH
Parameter
V
CC
Erase/Write Lock Voltage
V
CC
Supply Voltage
V
PP
During Read Operations
V
PP
During Erase/Program
RP, OE Unlock Voltage
Min
2.5
4.5
0
11.4
11.4
5.5
6.5
12.6
12.6
Max.
Unit
V
V
V
V
V
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V
±10%,
unless otherwise specified
JEDEC
Symbol
t
AVAV
t
ELQV
t
AVQV
t
GLQV
-
t
GLQX
t
ELQX
t
GHQZ
t
EHQZ
t
PHQV
Standard
Symbol
t
RC
t
CE
t
ACC
t
OE
t
OH
t
OLZ(1)(6)
t
LZ(1)(6)
t
DF(1)(2)
t
HZ(1)(2)
t
PWH
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
Output Hold from Address OE/CE Change
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
RP High to Output Delay
0
0
0
30
55
600
28F001-70
(8)
28F001-90
(7)
Min.
70
70
70
27
0
0
0
30
35
600
Max.
Min.
90
90
90
35
0
0
0
30
55
600
Max.
28F001-12
(7)
Min.
120
120
120
50
0
0
0
30
55
600
Max.
28F001-15
(7)
Min.
150
150
150
55
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. A.C. Testing Input/Output Waveform
(3)(4)(5)
2.4 V
INPUT PULSE LEVELS
0.45 V
0.8 V
2.0 V
REFERENCE POINTS
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
3.0 V
INPUT PULSE LEVELS
0.0 V
1.5 V
REFERENCE POINTS
5108 FHD F03
Testing Load Circuit (example)
1.3V
1N914
Testing Load Circuit (example)
1.3V
1N914
5108 FHD F03A
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
3.3K
DEVICE
UNDER
TEST
OUT
CL = 30 pF
CL INCLUDES JIG CAPACITANCE
5108 FHD F05
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2
5
Doc. No. 25071-00 2/98 F-1
分立器件
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
