Si 4 7 0 3 - B1 7
B
R O A D C A S T
F M R
A D I O
T
U N E R FOR
P
O R TA B L E
A
P P L I C A T I O N S
Features
RDS/RBDS Processor
Integrated crystal oscillator
GPIO1
GPIO2
GPIO3
17
10
V
IO
Applications
rN
NC
FMIP
RFGND
GND
RST
NC
ew
1
2
3
4
5
6
SEN
7
SCLK
20
This data sheet applies to
Si4703 Firmware 17 and greater
Worldwide FM band support
(76–108 MHz)
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
Seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis
(50/75 µs)
Pb-free/RoHS compliant
Pin Assignments
(Top View)
Si4703-GM
fo
Cellular handsets
MP3 players
Portable radios
USB FM radio
PDAs
Notebook PCs
Portable navigation
Automotive
Consumer electronics
19
18
d
Description
de
The Si4703 integrates the complete tuner function from antenna input to
stereo audio output for FM broadcast radio reception.
GND
PAD
en
Functional Block Diagram
Headphone
Cable
FMIP
RFGND
LNA
8
SDIO
9
RCLK
m
ec
om
Si4703
AMPLIFIER
DAC
LOUT
I
ADC
DSP
FILTER
DEMOD
MPX
AUDIO
Patents pending
Notes:
1.
To ensure proper operation and FM
receiver performance, follow the
guidelines in “AN231: Si4700/01/02/03
Headphone and Antenna Interface.”
Silicon Laboratories will evaluate
schematics and layouts for qualified
customers.
2.
Place Si4703 as close as possible to
antenna jack and keep the FMIP trace
as short as possible.
PGA
Q
ADC
DAC
ROUT
R
AGC
32.768 kHz
RCLK
VA
0 / 90
LOW-IF
GPIO
GPIO
VIO
N
ot
CONTROL
INTERFACE
TUNE
AFC
RDS
RST
SDIO
SCLK
SEN
2.7–5.5 V
VD
REG
XTAL
OSC
RSSI
Confidential Rev. 1.0 1/07
Copyright © 2007 by Silicon Laboratories
CONTROLLER
Si4703-B17
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
V
A
16
15 GND
14 LOUT
13 ROUT
12 GND
11 V
D
D
es
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control
interface
2.7 to 5.5 V supply voltage
Integrated LDO regulator
allows direct connection to
battery
3 x 3 mm 20-pin QFN package
Ordering Information:
See page 35.
ig
ns
Si4703-B17
2
N
ot
R
ec
om
m
en
Confidential Rev. 1.0
de
d
fo
rN
ew
D
es
ig
ns
Si4703-B17
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Pin Descriptions: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10. Package Outline: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11. PCB Land Pattern: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Confidential Rev. 1.0
3
Si4703-B17
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Digital Power Supply Power-Up
Rise Time
Analog Power Supply Power-Up
Rise Time
Interface Power Supply Power-Up
Rise Time
Ambient Temperature
Symbol
V
D
V
A
V
IO
V
DRISE
V
ARISE
V
IORISE
T
A
Test Condition
Min
2.7
2.7
1.5
25
25
25
–20
Typ
—
—
—
—
—
—
25
Max
5.5
5.5
3.6
—
—
—
Unit
V
V
V
µs
D
es
85
Unit
V
V
V
mA
V
°C
°C
V
pK
Table 2. Absolute Maximum Ratings
1,2
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Input Current
3
Input Voltage
3
Operating Temperature
Storage Temperature
RF Input Level
4
Symbol
V
D
V
A
V
IO
I
IN
de
d
en
V
IN
m
T
OP
om
T
STG
4
N
ot
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2.
The Si4703 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling and
assembly of this device should only be done at ESD-protected workstations.
3.
For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
4.
At RF input pins.
R
ec
Confidential Rev. 1.0
fo
–0.3 to (V
IO
+ 0.3)
–40 to 95
–55 to 150
0.4
rN
Value
–0.5 to 5.8
–0.5 to 5.8
–0.5 to 3.9
±10
ew
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
D
= V
A
= 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
ig
µs
°C
ns
µs
Si4703-B17
Table 3. DC Characteristics
(V
D
= V
A
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= –20 to 85 °C)
Parameter
Analog Supply Current
1
Analog Supply Current
1,2,3,4
Analog Powerdown Current
1,5,6
Digital Supply Current
1
Digital Supply Current
1,2,3,4
Digital Powerdown Current
1,5,6
Interface Supply Current
1
Interface Powerdown Current
1,5,6,7
High Level Input Voltage
8
Low Level Input Voltage
8
High Level Input Current
8
Low Level Input Current
8
High Level Output Voltage
9
Low Level Output Voltage
9
Symbol
I
A
I
A
I
PDA
I
D
I
D
I
PDD
I
IO
I
IO
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Test Condition
ENABLE = 1
ENABLE = 1
Low SNR level
ENABLE = 0
ENABLE = 1
ENABLE = 1
Low SNR level
ENABLE = 0
ENABLE = 1
SCLK, RCLK inactive
ENABLE = 0
Min
—
—
—
—
—
—
—
—
0.7 x V
IO
–0.3
Typ
13.4
14.2
2.4
5.3
5.0
2.1
400
0.5
—
Max
15.3
15.9
5
8.5
8.0
5
Unit
mA
mA
µA
mA
D
es
650
5
V
IO
+ 0.3
0.3 x V
IO
10
10
—
0.2 x V
IO
ew
—
—
—
—
—
V
IN
= 0 V,
V
IO
= 3.6 V
I
OUT
= 500 µA
I
OUT
= –500 µA
rN
V
IN
= V
IO
= 3.6 V
–10
–10
fo
0.8 x V
IO
—
N
ot
R
ec
om
Notes:
1.
Refer to Register 02h, "Power Configuration" on page 21 for ENABLE bit description.
2.
The LNA is automatically switched to higher current mode for optimum sensitivity in low SNR conditions.
3.
Analog and digital supply currents are simultaneously adjusted based on SNR level.
4.
Stereo and RDS functionality are disabled at low SNR levels.
5.
Specifications are guaranteed by characterization.
6.
Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 17.
7.
All GPIO pins are grounded.
8.
For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
9.
For output pins SDIO, GPIO1, GPIO2, and GPIO3.
m
en
Confidential Rev. 1.0
de
d
ig
ns
mA
µA
µA
µA
V
V
µA
µA
V
V
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
