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5962-8984004LA

产品描述EE PLD, 10ns, PAL-Type, CMOS, CDIP24, CERDIP-24
产品类别可编程逻辑器件    可编程逻辑   
文件大小83KB,共6页
制造商Lattice(莱迪斯)
官网地址http://www.latticesemi.com
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5962-8984004LA概述

EE PLD, 10ns, PAL-Type, CMOS, CDIP24, CERDIP-24

5962-8984004LA规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码DIP
包装说明CERDIP-24
针数24
Reach Compliance Codenot_compliant
ECCN代码EAR99
其他特性1 EXTERNAL CLOCK; REGISTER PRELOAD
架构PAL-TYPE
最大时钟频率58.8 MHz
JESD-30 代码R-GDIP-T24
长度31.875 mm
湿度敏感等级1
专用输入次数12
I/O 线路数量8
输入次数20
输出次数8
产品条款数64
端子数量24
最高工作温度125 °C
最低工作温度-55 °C
组织12 DEDICATED INPUTS, 8 I/O
输出函数MACROCELL
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP24,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)225
电源5 V
可编程逻辑类型EE PLD
传播延迟10 ns
认证状态Not Qualified
筛选级别MIL-STD-883
座面最大高度5.08 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度7.62 mm
Base Number Matches1

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GAL20V8/883
High Performance E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 62.5 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 12 mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• 50% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL
®
Devices with Full Function/
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
Functional Block Diagram
I/CLK
I
I
8
I
8
I
OLMC
I/O/Q
IMUX
CLK
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I
8
I/O/Q
OE
I/O/Q
I
OLMC
I
IMUX
I/OE
Description
The GAL20V8/883 is a high performance E
2
CMOS program-
mable logic devices processed in full compliance to MIL-STD-
883. This military grade device combines a high performance
CMOS process with Electrically Erasable (E
2
) floating gate tech-
nology to provide the highest speed/power performance available
in the 883 qualified PLD market.
The generic GAL architecture provides maximum design flexibil-
ity by allowing the Output Logic Macrocell (OLMC) to be config-
ured by the user. The GAL20V8/883 is capable of emulating all
standard 24-pin PAL
®
devices with full function/fuse map/para-
metric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
Pin Configuration
LCC
I/CLK
I/CLK
Vcc
I/O/Q
NC
I
I
I
CERDIP
1
24
Vcc
I
I/O/Q
I
I
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
I
I
2
28
5
26
25
I
I
I
I
I
I
I
I
GND
12
6
7
GAL20V8
Top View
23
I/O/Q
NC
GAL
20V8
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
13
I/OE
9
21
I/O/Q
I/O/Q
14
GND
NC
16
I/OE
I
19
18
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
20v8mil_02
1

5962-8984004LA相似产品对比

5962-8984004LA 5962-89840023A 5962-89840043A 5962-89840033A 5962-8984002LA GAL20V8B-20LD/883 GAL20V8B-10LD/883 GAL20V8B-10LR/883 GAL20V8B-15LR/883 GAL20V8B-20LR/883
描述 EE PLD, 10ns, PAL-Type, CMOS, CDIP24, CERDIP-24 EE PLD, 20ns, PAL-Type, CMOS, CQCC28, LCC-28 EE PLD, 10ns, PAL-Type, CMOS, CQCC28, LCC-28 EE PLD, 15ns, PAL-Type, CMOS, CQCC28, LCC-28 EE PLD, 20ns, PAL-Type, CMOS, CDIP24, CERDIP-24 EE PLD, 20ns, PAL-Type, CMOS, CDIP24, CERDIP-24 EE PLD, 10ns, PAL-Type, CMOS, CDIP24, CERDIP-24 EE PLD, 10ns, PAL-Type, CMOS, CQCC28, LCC-28 EE PLD, 15ns, PAL-Type, CMOS, CQCC28, LCC-28 EE PLD, 20ns, PAL-Type, CMOS, CQCC28, LCC-28
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
零件包装代码 DIP QLCC QLCC QLCC DIP DIP DIP QLCC QLCC QLCC
包装说明 CERDIP-24 LCC-28 LCC-28 LCC-28 CERDIP-24 CERDIP-24 CERDIP-24 LCC-28 LCC-28 LCC-28
针数 24 28 28 28 24 24 24 28 28 28
Reach Compliance Code not_compliant unknown unknown unknown not_compliant not_compliant unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
其他特性 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD 1 EXTERNAL CLOCK; REGISTER PRELOAD
架构 PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE
最大时钟频率 58.8 MHz 33.3 MHz 58.8 MHz 41.6 MHz 33.3 MHz 33.3 MHz 58.8 MHz 58.8 MHz 41.6 MHz 33.3 MHz
JESD-30 代码 R-GDIP-T24 S-CQCC-N28 S-CQCC-N28 S-CQCC-N28 R-GDIP-T24 R-GDIP-T24 R-GDIP-T24 S-CQCC-N28 S-CQCC-N28 S-CQCC-N28
长度 31.875 mm 11.43 mm 11.43 mm 11.43 mm 31.875 mm 31.875 mm 31.875 mm 11.43 mm 11.43 mm 11.43 mm
专用输入次数 12 12 12 12 12 12 12 12 12 12
I/O 线路数量 8 8 8 8 8 8 8 8 8 8
输入次数 20 20 20 20 20 20 20 20 20 20
输出次数 8 8 8 8 8 8 8 8 8 8
产品条款数 64 64 64 64 64 64 64 64 64 64
端子数量 24 28 28 28 24 24 24 28 28 28
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
组织 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O 12 DEDICATED INPUTS, 8 I/O
输出函数 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
封装主体材料 CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP QCCN QCCN QCCN DIP DIP DIP QCCN QCCN QCCN
封装等效代码 DIP24,.3 LCC28,.45SQ LCC28,.45SQ LCC28,.45SQ DIP24,.3 DIP24,.3 DIP24,.3 LCC28,.45SQ LCC28,.45SQ LCC28,.45SQ
封装形状 RECTANGULAR SQUARE SQUARE SQUARE RECTANGULAR RECTANGULAR RECTANGULAR SQUARE SQUARE SQUARE
封装形式 IN-LINE CHIP CARRIER CHIP CARRIER CHIP CARRIER IN-LINE IN-LINE IN-LINE CHIP CARRIER CHIP CARRIER CHIP CARRIER
电源 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
可编程逻辑类型 EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD
传播延迟 10 ns 20 ns 10 ns 15 ns 20 ns 20 ns 10 ns 10 ns 15 ns 20 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
筛选级别 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883
座面最大高度 5.08 mm 2.54 mm 2.54 mm 2.54 mm 5.08 mm 5.08 mm 5.08 mm 2.54 mm 2.54 mm 2.54 mm
最大供电电压 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO YES YES YES NO NO NO YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子形式 THROUGH-HOLE NO LEAD NO LEAD NO LEAD THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE NO LEAD NO LEAD NO LEAD
端子节距 2.54 mm 1.27 mm 1.27 mm 1.27 mm 2.54 mm 2.54 mm 2.54 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 DUAL QUAD QUAD QUAD DUAL DUAL DUAL QUAD QUAD QUAD
宽度 7.62 mm 11.43 mm 11.43 mm 11.43 mm 7.62 mm 7.62 mm 7.62 mm 11.43 mm 11.43 mm 11.43 mm
湿度敏感等级 1 1 1 1 1 - 1 1 1 1
JESD-609代码 - e0 e0 e0 - e0 - e0 e0 e0
端子面层 - Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) - TIN LEAD - Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)

 
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