DS1852
Optical Transceiver Diagnostic Monitor
www.maxim-ic.com
FEATURES
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Implements proposals of SFF-8472 at device address A2h
[Note: requires use of external EEPROM at address
A0h for full compliance.]
Top View
Scaleable four-input muxing analog-to-digital converter (ADC)
Direct-to-digital temperature converter
A
Programmable alarm and warning conditions
Temperature-compensated, programmable three-input muxing
B
fast comparator
C
Access temperature, data, and device control through a 2-wire
interface
D
Operates from 3V or 5V supplies
E
Packaging: 25-ball BGA
Operating temperature: -40°C to +100°C
Programming temperature: 0°C to +70°C
1 2 3 4 5
Three levels of security
5 x 5 BGA (0.8mm pitch)
127 bytes EEPROM for security level 1
128 bytes EEPROM for security level 2
Address space is GBIC compliant (with use of external EEPROM at device address A0h)
ORDERING INFORMATION
DS1852B-000
DS1852B-000+
DS1852B-000+T&R
DS1852B-000/T&R
+ Denotes lead-free package.
25-BALL BGA
25-BALL BGA LF
25-BALL BGA LF T&R
25-BALL BGA T&R
DESCRIPTION
The DS1852 transceiver monitor manages all system monitoring functions in a fiber optic data
transceiver module, in accordance with proposal SFF-8472. Its functions include 2-wire communications
with the host system, EEPROM memory for identification, tracking, and calibration, an ADC with four
muxing inputs, three fast comparators, and a temperature sensor to monitor an optical transceiver. The
DS1852 has programmable alarm and warning flags for all four analog-to-digital (A/D) conversion
values (three user analog inputs plus supply voltage) as well as the temperature. These conditions can be
used to determine critical parameters inside each module. The three fast comparators have temperature-
compensated programmability. The temperature dependencies of the trip points aid in assessing critical
conditions.
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011906
DS1852
The DS1852 is offered for sale free of any royalty or licensing fees.2
pn
ap.
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DS1852
PIN DESCRIPTIONS
Name Ball Locations
V
CC
GND
SDA
D2, D4, E3
B3, C2, C4, D3
B5
Description
Power-Supply Terminal.
The DS1852 will support supply voltages
ranging from +2.7V to +5.5V.
Ground Terminal
2-Wire Serial Data.
The serial data pin is for serial data transfer to and
from the DS1852. The pin is open drain and may be wire-OR’ed with
other open-drain or open-collector interfaces.
2-Wire Serial Clock.
The serial clock input is used to clock data into
the DS1852 on rising edges and clock data out on falling edges.
Analog Input Pin (Bias Value).
Input to A/D.
Analog Input Pin (Power Level).
Input to A/D.
Analog Input Pin (Received Power).
Input to A/D.
Address Select Pin.
If set to logic 0, the device address is A0h. If set to
logic 1, the value in Table 3, byte D0h determines the chip address
(factory default is A2h). For SFF-8472 compliance, this pin should be
connected high.
Digital Input Pin (TX Disable).
Digital input for mirroring in memory
map.
Digital Input Pin (Rate Select).
Digital input for mirroring in memory
map.
Digital Input Pin (TX Fault).
Digital input for mirroring in memory
map.
Digital Input Pin (LOS).
Digital input for mirroring in memory map.
No Connect
SCL
B
in
P
in
R
in
A5
A3
D1
A2
ASEL
B2
D
in
RS
in
F
in
L
in
NC
C5
B4
E5
A1
A4, B1, C1, D5,
E1, E2, E4, C3
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DS1852
DS1852 BLOCK DIAGRAM
Figure 1
V
CC
OUTPUT REGISTERS
B
IN
P
IN
R
IN
Control
3:1
MUX
Control
Control
FAST
TRIP
5:1
MUX
T
ADC
V
B
P
R
FAST
ALARM
WARN
ALARM
and
WARN
TEMP
SENSOR
Control
Control
SDA
SCL
2-WIRE
Interface
EEPROM
CUSTOMER
EEPROM
CONTROL
SETTINGS
CONTROL
LOGIC
Control
Control
Signals
GND
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DS1852
DEVICE OPERATION
Security
To prevent accidental overwrites of key device data, a data lockout feature is incorporated. A 32-bit
password provides access to the “manufacturer” memory locations. These locations are in addition to the
unprotected “user” memory locations:
1) User—This is the default state after power-up; it allows read access to standard IEEE identity table
and standard monitoring and status functions.
2) Manufacturer Level 1—This allows access to customer data table and some selected setups (password
1).
3) Manufacturer Level 2—This allows access to all memory, settings, and features (password 2).
The level 1 password is located in Table 03h EEPROM (bytes D3h to D6h) and may be changed by
gaining access through the level 2 password.
The level 2 password is set in protected EEPROM and is programmed during factory test.
During power-up, the 32-bit password entry (addresses 7Bh to 7Eh) is set to all 1s. This is the value that
is compared to the level 1 password entry in Table 03h to grant level 1 access. Therefore, the level 1
password should not be set to all 1s or the user will gain level 1 access after each power-on.
By default, both passwords are factory preset to 00h.
To gain access to a security level, a 4-byte password is written into Table 00h, bytes 7Bh to 7Eh. If the
written data matches one of the passwords, that corresponding level of access is granted until the
password entry is changed or the power is cycled. Entering the level 2 password allows access to both
the level 1 data and the level 2 data. The 4-byte password is write-only.
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