A3958
DMOS Full-Bridge PWM Motor Driver
Features and Benefits
▪
±2 A, 50 V continuous output rating
▪
Low r
DS(on)
outputs (270 mΩ, typical)
▪
Programmable mixed, fast, and slow current-decay modes
▪
Serial interface controls chip functions
▪
Synchronous rectification for low power dissipation
▪
Internal UVLO and thermal-shutdown circuitry
▪
Crossover-current protection
Description
Designed for pulse width modulated (PWM) current control of
DC motors, the A3958 is capable of continuous output currents
to ±2 A and operating voltages to 50 V. Internal fixed off-time
PWM current-control timing circuitry can be programmed via
a serial interface to operate in slow, fast, and mixed current-
decay modes.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM-control signals. The ENABLE input
can be programmed via the serial port to PWM the bridge in
fast or slow current decay. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during
PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover-current protection. Special power-up
sequencing is not required.
Packages:
Package B, 24-pin DIP
with exposed tabs
Package LB, 24-pin SOIC
with internally fused pins
Not to scale
The A3958 is supplied in a choice of two power packages, a
24-pin plastic DIP with exposed thermal tabs (package suffix
‘B’), and a 24-pin SOIC with internally fused pins (package
suffix ‘LB’). In both cases, the power pins are at ground potential
and need no electrical isolation. Each package type is lead (Pb)
free, with 100% matte tin leadframe.
Functional Block Diagram
V
DD
LOGIC
SUPPLY
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
V
BB
+
CP1
CP2
LOAD
SUPPLY
BANDGAP
REGULATOR
V
REG
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
CONTROL LOGIC
OUT
A
PHASE
ENABLE
SYNC RECT MODE
SYNC RECT DISABLE
PWM MODE INT
PWM MODE EXT
MODE
PHASE
ENABLE
GATE DRIVE
CP
OUT
B
SENSE
ZERO
CURRENT
DETECT
C
S
R
S
FIXED OFF
OSC
PROGRAMMABLE
BLANK
DECAY
PWM TIMER
SLEEP
MODE
CLOCK
DATA
STROBE
RANGE
CURRENT
SENSE
RANGE
SERIAL
PORT
REFERENCE
BUFFER &
DIVIDER
REF
V
REF
Dwg. FP-048
29319.31F
A3958
Selection Guide
Part Number
Packing
DMOS Full-Bridge PWM Motor Driver
Package
A3958SB-T*
24-pin DIP with exposed thermal tabs
15 per Tube
A3958SLBTR-T
24-pin SOICW with internally fused pins
1000 per reel
Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates
that sale of the variant is currently restricted to existing customer applications. The variant should not be
purchased for new design applications because obsolescence in the near future is probable. Samples are no
longer available. Status change: May 4, 2009.
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic Supply Voltage
Input Voltage
Sense Voltage
Reference Voltage
Output Current
Symbol
V
BB
V
DD
V
IN
V
S
V
REF
I
OUT
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions, do
not exceed the specified current rating or a junction tempera-
ture of 150°C.
B package, per SEMI G42-88 Specification, T
A
= 25°C
LB package, per SEMI G42-88 Specification, T
A
= 25°C
Range S
Fault conditions that produce excessive junction temperature
will activate the device’s thermal shutdown circuitry. These
conditions can be tolerated but should be avoided.
Notes
Rating
50
7.0
–0.3 to V
CC
+ 0.3
0.5
2.7
±2.0
3.1
1.6
–20 to 85
150
–55 to 150
Units
V
V
V
V
V
mA
W
W
ºC
ºC
ºC
Package Power Dissipation
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
P
D
T
A
T
J
(max)
T
stg
Thermal Characteristics
Characteristic
Package Thermal Resistance, Junction
to Ambient
Package Thermal Resistance, Junction
to Tab
Symbol
R
θJA
R
θJT
ALLOWABLE PACKAGE POWER DISSIPATION (W)
Test Conditions*
2
B Package, single-layer PCB, 1 in. 2-oz. exposed copper
Value
40
77
6
Units
ºC/W
ºC/W
ºC/W
LB Package, single-layer PCB, minimal exposed copper area
*Additional thermal information available on Allegro website.
4
R
JT
= 6.0 C/W
3
SUFFIX 'B', R
JA
= 40 C/W
2
1
SUFFIX 'LB', R
JA
= 77 C/W
0
25
50
75
100
TEMPERATURE IN C
125
150
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Copyright © 2000, 2002 Allegro MicroSystems, Inc.
A3958
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Load Supply Current
V
BB
I
DSS
r
DS(on)
V
F
I
BB
Operating
During sleep mode
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= -2 A
Sink driver, I
OUT
= 2 A
Source diode, I
F
= -2 A
Sink diode, I
F
= 2 A
f
PWM
< 50 kHz
Charge pump on, outputs disabled
Sleep Mode
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
(all inputs except ENABLE)
ENABLE Input Current
OSC input frequency
OSC input duty cycle
OSC input hysteresis
Input Hysteresis
Reference Input Volt. Range
Reference Input Current
Comparator Input Offset Volt.
V
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
I
IN(1)
I
IN(0)
f
OSC
dc
OSC
–
–
V
REF
I
REF
V
IO
V
IN
= 2.0 V
V
IN
= 0.8 V
V
IN
= 2.0 V
V
IN
= 0.8 V
Operating
Operating
Operating
All digital inputs except OSC
Operating
V
REF
= 2.5 V
V
REF
= 0 V
Operating
4.5
2.0
–
–
–
–
–
2.9
40
200
50
0.0
–
–
5.0
–
–
<1.0
<-2.0
40
16
–
–
–
–
–
–
0
5.5
–
0.8
20
-20
100
40
6.1
60
400
100
2.6
±0.5
±5.0
V
V
V
μA
μA
μA
μA
MHz
%
mV
mV
V
μA
mV
20
0
–
–
–
–
–
–
–
–
–
–
–
<1.0
<-1.0
270
270
1.2
1.2
4.0
2.0
–
50
50
20
-20
300
300
1.6
1.6
7.0
5.0
20
V
V
μA
μA
mΩ
mΩ
V
V
mA
mA
μA
Symbol Test Conditions
Min.
Typ. Max.
Units
Continued next page …
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3958
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
=
0.5 V, f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Control Logic
Buffer Input Offset Volt.
Reference Divider Ratio
Propagation Delay Times
V
IO
–
t
pd
D14 = High
D14 = Low
PWM change to source ON
PWM change to source OFF
PWM change to sink ON
PWM change to sink OFF
Phase change to sink ON
Phase change to sink OFF
Phase change to source ON
Phase change to source OFF
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
T
J
∆T
J
UVLO
∆UVLO
I
DD
f
PWM
< 50 kHz
Sleep Mode, Inputs < 0.5 V
Increasing V
DD
–
9.9
4.95
–
–
–
–
–
–
–
–
–
–
3.90
0.05
–
–
0
10
5.0
600
100
600
100
600
100
600
100
165
15
4.2
0.10
6.0
–
±15
10.2
5.05
–
–
–
–
–
–
–
–
–
–
4.45
–
10
2.0
mV
–
–
ns
ns
ns
ns
ns
ns
ns
ns
°C
°C
V
V
mA
mA
Symbol Test Conditions
Min.
Typ. Max.
Units
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3958
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Serial Interface.
The A3958 is controlled via a 3-wire
(clock, data, strobe) serial port. The programmable
functions allow maximum
fl
exibility in configuring the
PWM to the motor drive requirements. The serial data is
clocked in starting with D19.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
Function
Blank Time LSB
Blank Time MSB
Off Time LSB
Off Time Bit 1
Off Time Bit 2
Off Time Bit 3
Off Time MSB
Fast Decay Time LSB
Fast Decay Time Bit 1
Fast Decay Time Bit 2
Fast Decay Time MSB
Sync. Rect. Mode
Sync. Rect. Enable
External PWM Mode
Enable
Phase
Reference Range Select
Internal PWM Mode
Test Use Only
Sleep Mode
D7 – D10 Fast Decay Time.
A four-bit word sets the
fast-decay portion of the
fi
xed-off time for the internal
PWM control circuitry. This will only have impact if the
mixed-decay mode is selected (via bit D17 and the MODE
input terminal). For t
fd
> t
off
, the device will effectively
operate in the fast-decay mode. The fast decay portion is
defined by
t
fd
= (8[1 + N]/f
osc
) - 1/f
osc
where N = 0 … 15
For example, with an oscillator frequency of 4 MHz, the
fast decay time will be adjustable from 1.75
μs
to
31.75
μs
in increments of 2
μs.
D11 Synchronous Rectification Mode.
The active
mode prevents reversal of load current by turning off
synchronous rectification when a zero current level is
detected. The passive mode will allow reversal of current
but will turn off the synchronous rectifier circuit if the load
current inversion ramps up to the current limit set by
V
REF
/R
S
.
D11
0
1
Mode
Active
Passive
D12 Synchronous Rectification Enable.
D12
0
1
Synchronous Rect.
Disabled
Enabled
D0 – D1 Blank Time.
The current-sense comparator is
blanked when any output driver is switched on, according
to the table below. f
osc
is the oscillator input frequency.
D1
0
0
1
1
D0
0
1
0
1
Blank Time
4/f
osc
6/f
osc
12/f
osc
24/f
osc
D13 External PWM Decay Mode.
Bit D13 determines
the current-decay mode when using ENABLE chopping
for external PWM current control.
D13
0
1
Mode
Fast
Slow
D2 – D6 Fixed-Off Time.
A
fi
ve-bit word sets the
fi
xed-
off time for internal PWM current control. The off time is
defined by
t
off
= (8[1 + N]/f
osc
) - 1/f
osc
where N = 0 … 31
For example, with an oscillator frequency of 4 MHz, the
off time will be adjustable from 1.75
μs
to 63.75
μs
in
increments of 2
μs.
D14 Enable Logic.
Bit D14, in conjunction with
ENABLE, determines if the output drivers are in the
chopped (OFF)(ENABLE = D14) or ON (ENABLE
≠
D14) state.
ENABLE
0
1
0
1
D14
0
0
1
1
Mode
Chopped
On
On
Chopped
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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