INTEGRATED CIRCUITS
74LV109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 Apr 20
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
FEATURES
•
Optimized for low voltage applications: 1.0 to 3.6 V
•
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
•
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
•
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
•
Output capability: standard
•
I
CC
category: flip-flops
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LV109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (S
D
) and reset
(R
D
) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation.
The JK design allows operation as a D-type flip-flop by tying the
J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
=t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
V
I
= GND to V
CC1
CONDITIONS
TYPICAL
14
12
12
77
3.5
20
UNIT
ns
MHz
pF
pF
C
L
= 15 pF;
V
CC
= 3.3 V
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV109 N
74LV109 D
74LV109 DB
74LV109 PW
NORTH AMERICA
74LV109 N
74LV109 D
74LV109 DB
74LV109PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
1R
D
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2R
2J
2K
2CP
2S
D
D
PIN DESCRIPTION
PIN
NUMBER
1, 15
2, 14, 3, 13
4, 12
5, 11
6, 10
7, 9
8
16
SYMBOL
1R
D
, 2R
D
1J, 2J,
1K, 2K
1CP, 2CP
1S
D,
2S
D
1Q, 2Q
1Q, 2Q
GND
V
CC
FUNCTION
Asynchronous reset input
(active LOW)
Synchronous inputs; flip-flops 1 and 2
Clock input (LOW-to-HIGH,
edge-triggered)
Asynchronous set inputs
(active LOW)
True flip-flop outputs
Complement flip-flop outputs
Ground (0 V)
Positive supply voltage
853-1986 19255
1J
1K
1CP
1S D
1Q
1Q
GND
2Q
2Q
SV00517
1998 Apr 20
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
LOGIC SYMBOL (IEEE/IEC)
5
S
2
1J
4
C1
3
1K
1
R
15
R
7
13
1K
12
C1
9
6
14
1J
11
S
10
FUNCTIONAL DIAGRAM
5
1S
D
1J
S
D
J
Q
FF1
Q
R
D
1 1R
D
11 2S
D
S
D
(b)
14 2J J
Q
FF2
Q
R
D
2Q
9
2Q 10
1Q
7
1Q
6
2
4 1CP CP
3
1K
K
(a)
SV00519
12 2CP
CP
LOGIC SYMBOL
5 11
1S D 2S D
13 2K K
15 2R
D
SV00520
2 1J
14 2J
4 1CP
12 2CP
3 1K
13 2K
J
Q
1Q 6
2Q 10
CP
1Q 7
K
Q
2Q 9
1R D 2R D
1 15
SV00518
LOGIC DIAGRAM
K
C
C
C
C
Q
Q
J
C
S
C
C
C
R
C
C
CP
SV00521
1998 Apr 20
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
FUNCTION TABLE
INPUTS
OPERATING MODES
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load “0” (reset)
Load “1” (set)
Hold “no change”
nS
D
L
H
L
H
H
H
H
nR
D
H
L
L
H
H
H
H
nCP
X
X
X
↑
↑
↑
↑
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
nQ
H
L
H
q
L
H
q
OUTPUTS
nQ
L
H
H
q
H
L
q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
↑
= LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
Input voltage
Output voltage
Operating ambient temperature range in free air
Input rise and fall times except for
Schmitt-trigger inputs
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
PARAMETER
DC supply voltage
CONDITIONS
See Note 1
MIN
1.0
0
0
-40
-40
–
–
–
–
–
–
TYP.
3.3
–
–
MAX
3.6
V
CC
V
CC
+85
+125
500
200
100
UNIT
V
V
V
°C
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 3.6V.
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
"I
IK
"I
OK
"I
O
"I
GND
,
"I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
– standard outputs
Storage temperature range
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +4.6
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
mW
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 20
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
V
CC
= 1.2 V
V
IH
HIGH l
level I
l Input
t
voltage
V
CC
= 2.0 V
V
CC
= 2.7 to 3.6 V
V
CC
= 1.2 V
V
IL
LOW l
level I
l Input
t
voltage
V
CC
= 2.0 V
V
CC
= 2.7 to 3.6 V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
O
OH
HIGH level output
voltage; all outputs
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
OH
HIGH level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
–I
O
= 6mA
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
O
OL
LOW level output
voltage; all outputs
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
OL
LOW level output
voltage;
STANDARD
outputs
Input leakage
current
Quiescent supply
current; flip-flops
Additional
quiescent supply
current per input
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
1.8
2.5
2.8
2.40
1.2
2.0
2.7
3.0
2.82
0
0
0
0
0.25
0.2
0.2
0.2
0.40
0.2
0.2
0.2
0.50
V
V
1.8
2.5
2.8
2.20
V
V
0.9
1.4
2.0
0.3
0.6
0.8
-40°C to +85°C
TYP
1
MAX
-40°C to +125°C
MIN
0.9
1.4
2.0
0.3
0.6
0.8
V
V
MAX
UNIT
I
I
I
CC
∆I
CC
V
CC
= 3.6 V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7 V to 3.6 V; V
I
= V
CC
– 0.6 V
1.0
20.0
500
1.0
80
850
µA
µA
µA
NOTE:
1. All typical values are measured at T
amb
= 25°C.
AC CHARACTERISTICS
GND
=
0V; t
r
=
t
f
≤
2.5ns; C
L
=
50pF; R
L
=
1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
V
CC
(V)
1.2
t
PHL
/t
PLH
Propagation delay
g
y
nCP to nQ, nQ
Figure 1
2.0
2.7
3.0 to 3.6
1.2
t
PLH
Propagation delay
g
y
nS
D
to nQ
Figure 2
2.0
2.7
3.0 to 3.6
MIN
LIMITS
–40 to +85
°C
TYP
1
90
31
23
18
2
55
19
14
10
2
36
26
21
44
33
26
ns
58
43
34
70
51
41
ns
MAX
–40 to +125
°C
MIN
MAX
UNIT
1998 Apr 20
5
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