74AUP1G97
Low-power configurable multiple function gate
Rev. 8 — 15 August 2012
Product data sheet
1. General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
SOT1115
SOT1202
4. Marking
Table 2.
Marking
Marking code
[1]
aV
aV
aV
aV
aV
Type number
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
4
B
1
A
Y
C
6
001aad998
Fig 1.
Logic symbol
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 August 2012
2 of 22
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
74AUP1G97
74AUP1G97
B
GND
1
2
6
5
C
GND
V
CC
A
A
3
001aad999
B
1
6
C
B
GND
74AUP1G97
1
2
3
6
5
4
C
V
CC
Y
2
5
V
CC
3
4
Y
A
4
Y
001aae000
001aae001
Transparent top view
Transparent top view
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
H
H
L
H
L
H
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 August 2012
3 of 22
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 6
see
Figure 7
see
Figure 7
see
Figure 8
see
Figure 8
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
V
CC
B
B
Y
A
A
C
001aae002
V
CC
1
A
C
Y
A
2
3
6
5
4
Y
001aae003
1
2
3
6
5
4
C
C
Y
Fig 5.
2-input MUX
Fig 6.
2-input AND gate
V
CC
V
CC
A
C
Y
1
2
6
5
4
C
B
C
Y
B
1
2
6
5
4
C
A
C
Y
A
3
Y
001aae004
B
C
Y
3
Y
001aae005
Fig 7.
2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig 8.
2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
V
CC
B
B
C
Y
1
2
3
6
5
C
4
Y
3
001aae006
V
CC
C
1
Y
2
6
5
4
Y
001aae007
C
Fig 9.
2-input OR gate
Fig 10. Inverter
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 August 2012
4 of 22
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aae008
Fig 11. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down
mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
40
Max
3.6
3.6
V
CC
3.6
+125
Unit
V
V
V
V
C
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 August 2012
5 of 22
测试/测量
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
