v5.9
ProASIC
PLUS®
Flash Family FPGAs
High Performance Routing Hierarchy
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
®
Features and Benefits
High Capacity
Commercial and Industrial
•
•
•
•
•
•
•
•
•
•
•
•
75,000 to 1 Million System Gates
27 K to 198 Kbits of Two-Port SRAM
66 to 712 User I/Os
300, 000 to 1 Million System Gates
72 K to 198 Kbits of Two Port SRAM
158 to 712 User I/Os
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
®
)
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
APA075
75,000
3,072
27 k
12
2
2
4
24
158
Yes
Yes
100, 144
208
–
144
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
100
208
456
144, 256
I/O
Schmitt-Trigger Option on Every Input
2.5 V / 3.3 V Support with Individually-Selectable Voltage
and Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin-Compatible Packages across the ProASIC
PLUS
Family
PLL with Flexible Phase, Multiply/Divide, and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate
Optimization
In-System Programming (ISP) via JTAG Port
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
Military
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow
Performance
•
•
•
•
•
•
•
ISP Support
•
•
•
Secure Programming
Low Power
SRAMs and FIFOs
Table 1 •
ProASIC
PLUS
Product Profile
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
CQFP
2
CCGA/LGA
2
Notes:
APA300
1
300,000
8,192
72 k
32
2
2
4
32
290
Yes
Yes
–
208
456
144, 256
208, 352
APA450
450,000
12,288
108 k
48
2
2
4
48
344
Yes
Yes
–
208
456
144, 256, 484
APA600
1
600,000
21,504
126 k
56
2
2
4
56
454
Yes
Yes
–
208
456
256, 484, 676
208, 352
624
APA750
750,000
32,768
144 k
64
2
2
4
64
562
Yes
Yes
–
208
456
676, 896
APA1000
1
1,000,000
56,320
198 k
88
2
2
4
88
712
Yes
Yes
–
208
456
896, 1152
208, 352
624
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
D e c e m b er 2 0 0 9
© 2009 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
ProASIC
PLUS
Flash Family FPGAs
Ordering Information
APA1000
_
FG
G
1152
I
Application (Ambient Temperature Range)
Blank = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PP = Pre-production
ES = Engineering Silicon (room temperature only)
M = Military (–55°C to 125°C)
B = MIL-STD-883 Class B
Package Lead Count
Lead-free packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
BG = Plastic Ball Grid Array (1.27 mm pitch)
CQ = Ceramic Quad Flat Pack (1.05 mm pitch)
CG = Ceramic Column Grid Array (1.27 mm pitch)
LG = Land Grid Array (1.27 mm pitch)
Speed Grade
Blank = Standard Speed
Part Number
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
=
=
=
=
=
=
=
75,000 Equivalent System Gates
150,000 Equivalent System Gates
300,000 Equivalent System Gates
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
1,000,000 Equivalent System Gates
ii
v5.9
ProASIC
PLUS
Flash Family FPGAs
Device Resources
User I/Os
2
Commercial/Industrial
Military/MIL-STD-883B
CCGA/
LGA
CQFP
CQFP
TQFP
3
TQFP
3
PQFP
3
PBGA
3
FBGA
3
FBGA
3
FBGA
3
FBGA
3
FBGA
3
FBGA
3
100-Pin 144-Pin 208-Pin 456-Pin 144-Pin 256-Pin 484-Pin 676-Pin 896-Pin 1152-Pin 208-Pin 352-Pin 624-Pin
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
66
66
107
158
158
158
5
158
158
5
158
158
5
242
290
5
344
356
5
356
356
5
100
100
100
5
100
186
4
186
4, 5
186
4
186
4, 5
344
4
370
4
454
454
562
6
642
5, 6
712
6
158
248
440
158
248
440
158
248
Notes:
1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid
Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array
2. Each pair of PECL I/Os is counted as one user I/O.
3. Available in RoHS compatible packages. Ordering code is "G."
4. FG256 and FG484 are footprint-compatible packages.
5. Military Temperature Plastic Package Offering
6. FG896 and FG1152 are footprint-compatible packages.
General Guideline
Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee
performance beyond the limits specified within the datasheet.
v5.9
iii
ProASIC
PLUS
Flash Family FPGAs
Temperature Grade Offerings
Package
TQ100
TQ144
PQ208
BG456
FG144
FG256
FG484
FG676
FG896
FG1152
CQ208
CQ352
CG624
Note:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
M, B
M, B
M, B
M, B
M, B
C, I
APA075
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I, M
C, I, M
C, I, M
C, I, M
C, I
C, I
C, I
C, I
C, I
C, I, M
C, I, M
C, I, M
C, I
C, I
C, I, M
C, I
M, B
M, B
M, B
C, I, M
C, I, M
C, I
C, I
C, I, M
C, I, M
APA150
C, I
APA300
APA450
APA600
APA750
APA1000
Speed Grade and Temperature Matrix
Std.
C
I
M, B
Note:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
✓
✓
✓
iv
v5.9
ProASIC
PLUS
Flash Family FPGAs
Device Family Overview
The ProASIC
PLUS
family of devices, Actel’s second-
generation family of flash FPGAs, offers enhanced
performance over Actel’s ProASIC family. It combines the
advantages of ASICs with the benefits of programmable
devices through nonvolatile flash technology. This
enables engineers to create high-density systems using
existing ASIC or FPGA design flows and tools. In addition,
the ProASIC
PLUS
family offers a unique clock conditioning
circuit based on two on-board phase-locked loops (PLLs).
The family offers up to one million system gates,
supported with up to 198 kbits of two-port SRAM and up
to 712 user I/Os, all providing 50 MHz PCI performance.
Advantages
to
the
designer
extend
beyond
performance. Unlike SRAM-based FPGAs, four levels of
routing hierarchy simplify routing, while the use of flash
technology allows all functionality to be live at power-
up. No external boot PROM is required to support device
programming. While on-board security mechanisms
prevent
access
to
the
program
information,
reprogramming can be performed in-system to support
future design iterations and field upgrades. The device’s
architecture mitigates the complexity of ASIC migration
at higher user volume. This makes ProASIC
PLUS
a cost-
effective solution for applications in the networking,
communications, computing, and avionics markets.
The ProASIC
PLUS
family achieves its nonvolatility and
reprogrammability through an advanced flash-based
0.22
μm
LVCMOS process with four layers of metal.
Standard CMOS design techniques are used to
implement logic and control functions, including the
PLLs and LVPECL inputs. This results in predictable
performance compatible with gate arrays.
The ProASIC
PLUS
architecture provides granularity
comparable to gate arrays. The device core consists of a
Sea-of-Tiles
™
. Each tile can be configured as a flip-flop,
latch, or three-input/one-output logic function by
programming the appropriate Flash switches. The
combination of fine granularity, flexible routing
resources, and abundant flash switches allows 100%
utilization and over 95% routability for highly congested
designs. Tiles and larger functions are interconnected
through a four-level routing hierarchy.
Embedded two-port SRAM blocks with built-in FIFO/RAM
control logic can have user-defined depths and widths.
Users can also select programming for synchronous or
asynchronous operation, as well as parity generations or
checking.
The unique clock conditioning circuitry in each device
includes two clock conditioning blocks. Each block
provides a PLL core, delay lines, phase shifts (0° and
180°), and clock multipliers/dividers, as well as the
circuitry needed to provide bidirectional access to the
PLL. The PLL block contains four programmable
frequency dividers which allow the incoming clock signal
to be divided by a wide range of factors from 1 to 64.
The clock conditioning circuit also delays or advances the
incoming reference clock up to 8 ns (in increments of
0.25 ns). The PLL can be configured internally or
externally during operation without redesigning or
reprogramming the part. In addition to the PLL, there
are two LVPECL differential input pairs to accommodate
high-speed clock and data inputs.
To support customer needs for more comprehensive,
lower-cost, board-level testing, Actel’s ProASIC
PLUS
devices are fully compatible with IEEE Standard 1149.1
for test access port and boundary-scan test architecture.
For more information concerning the flash FPGA
implementation, please refer to the
"Boundary Scan
(JTAG)" section on page 2-8.
ProASIC
PLUS
devices are available in a variety of high-
performance plastic packages. Those packages and the
performance features discussed above are described in
more detail in the following sections.
v5.9
1-1
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