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CDCE937, CDCEL937
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
CDCEx937 Flexible Low Power LVCMOS Clock Generator
With SSC Support For EMI Reduction
1 Features
1
2 Applications
D-TVs, STBs, IP-STBs, DVD Players, DVD
Recorders, and Printers
•
•
•
•
•
•
•
•
•
•
•
Member of Programmable Clock Generator
Family
– CDCEx913: 1-PLL, 3 Outputs
– CDCEx925: 2-PLL, 5 Outputs
–
CDCEx937: 3-PLL, 7 Outputs
– CDCEx949: 4-PLL, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Setting
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Free Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 60 ps)
Separate Output Supply Pins
– CDCE937: 3.3 V and 2.5 V
– CDCEL937: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for Example, SSC Selection,
Frequency Switching, Output Enable or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth™,
WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
3 Description
The CDCE937 and CDCEL937 devices are modular
PLL-based
low
cost,
high-performance,
programmable clock synthesizers, multipliers and
dividers. They generate up to 7 output clocks from a
single input frequency. Each output can be
programmed in-system for any clock frequency up to
230 MHz, using up to three independent configurable
PLLs.
The CDCEx937 has separate output supply pins,
VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V
to 3.3 V for CDCE937.
The input accepts an external crystal or LVCMOS
clock signal. If an external crystal is used, an on-chip
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from 0 to
20 pF. Additionally, an on-chip VCXO is selectable
which allows synchronization of the output frequency
to an external control signal, that is, PWM signal.
Device Information
(1)
PART NUMBER
CDCE937,
CDCEL937
PACKAGE
TSSOP (20)
BODY SIZE (NOM)
6.50 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Schematic
Ethernet PHY
CDCE(L)9xx Clock
WiFi
25 MHz
USB Controller
FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE937, CDCEL937
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements: CLK_IN .................................
Timing Requirements: SDA/SCL ..............................
EEPROM Specification .............................................
Typical Characteristics ..............................................
1
1
1
2
4
5
5
5
5
6
6
8
8
8
9
8.4 Device Functional Modes........................................
15
8.5 Programming...........................................................
16
8.6 Register Maps .........................................................
17
9
Application and Implementation
........................
24
9.1 Application Information............................................
24
9.2 Typical Application ..................................................
24
10 Power Supply Recommendations
.....................
29
11 Layout...................................................................
29
11.1 Layout Guidelines .................................................
29
11.2 Layout Example ....................................................
30
12 Device and Documentation Support
.................
31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
7
8
Parameter Measurement Information
................
10
Detailed Description
............................................
11
8.1 Overview .................................................................
11
8.2 Functional Block Diagram .......................................
12
8.3 Feature Description.................................................
12
13 Mechanical, Packaging, and Orderable
Information
...........................................................
32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2010) to Revision G
•
Page
Added
ESD Ratings
table,
Feature Description
section,
Device Functional Modes, Application and Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device and Documentation Support
section, and
Mechanical, Packaging, and Orderable Information
section ..................................................................................................
1
Changed
Applications.............................................................................................................................................................
1
Changed Thermal Resistance Junction to Ambient, R
θJA
, values in
Thermal Information
From: 89 (0 lfm), 75 (150
lfm), 74 (200 lfm), 74 (250 lfm), and 69 (500 lfm) To: 89.04 ..................................................................................................
6
Deleted
Input Capacitance
figure .........................................................................................................................................
19
•
•
•
Changes from Revision E (October 2009) to Revision F
•
•
•
Page
Added PLL settings limits: 16
≤
q
≤
63, 0
≤
p
≤
7, 0
≤
r
≤
511, 0 < N < 4096 foot to PLL1, PLL2, and PLL3 Configure
Register Table ......................................................................................................................................................................
20
Changed 100 MHz < ƒ
VCO
> 200 MHz; TO 80 MHz
≤
ƒ
VCO
≤
230 MHz; and changed 0
≤
p
≤
7 TO 0
≤
p
≤
4 ...................
26
Changed under Example, fifth row, N", 2 places TO N' .......................................................................................................
26
Changes from Revision D (September 2009) to Revision E
•
Page
Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments
sales or marketing representative for more information. ......................................................................................................
14
Changes from Revision C (January 2009) to Revision D
•
Page
Added Note 3: SDA and SCL can go up to 3.6 V as stated in the
Recommended Operating Conditions
table ...................
5
2
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links:
CDCE937 CDCEL937
CDCE937, CDCEL937
www.ti.com
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
Changes from Revision B (December 2007) to Revision C
•
Page
Changed
Generic Configuration Register
table SLAVE_ADR default value From: 00b To: 01b .........................................
18
Changes from Revision A (September 2007) to Revision B
•
•
•
Page
Changed Terminal Functions Table - the pin numbers to correspond with pin outs on the package....................................
4
Changed
Generic Configuration Register
table RID default From: 0h To: Xb .....................................................................
18
Added note to PWDN description to
Generic Configuration Register
table .........................................................................
18
Changes from Original (August 2007) to Revision A
•
Page
Changed the data sheet status From: Product Preview To: Production data ........................................................................
1
Copyright © 2007–2016, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links:
CDCE937 CDCEL937
CDCE937, CDCEL937
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
www.ti.com
5 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
Xin/CLK
S0
VDD
VCtrl
GND
Vddout
Y4
Y5
GND
Vddout
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Xout
SDA/S1
SCL/S2
Y1
GND
Y2
Y3
Vddout
Y6
Y7
Not to scale
Pin Functions
PIN
NAME
GND
SCL/S2
SDA/S1
S0
V
Ctrl
V
DD
Vddout
Xin/CLK
Xout
Y1
Y2
Y3
Y4
Y5
Y6
Y7
(1)
NO.
5, 9, 16
18
19
2
4
3
6, 10, 13
1
20
17
15
14
7
8
12
11
TYPE
(1)
G
I
I/O
I
I
P
P
I
O
O
O
O
O
O
O
O
Ground
SCL: Serial clock input (default configuration), LVCMOS; Internal pullup 500k;
S2: User programmable control input; LVCMOS inputs; Internal pullup 500k
SDA: Bi-directional serial data input/output (default configuration). LVCMOS; Internal pullup 500k;
S1: User programmable control input; LVCMOS inputs; Internal pullup 500k
User programmable control input S0; LVCMOS inputs; Internal pullup 500k
VCXO control voltage, leave open or pullup (approximately 500k) when not used
1.8-V power supply for the device
CDCEL937: 1.8-V supply for all outputs
CDCE937: 3.3-V or 2.5-V supply for all outputs
Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus)
Crystal oscillator output, leave open or pullup (~500k) when not used
LVCMOS outputs
LVCMOS outputs
LVCMOS outputs
LVCMOS outputs
LVCMOS outputs
LVCMOS outputs
LVCMOS outputs
DESCRIPTION
G= Ground, I = Input, O = Output, P = Power
4
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links:
CDCE937 CDCEL937
CDCE937, CDCEL937
www.ti.com
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Supply voltage, V
DD
Input voltage, V
I
(2) (3)
MAX
2.5
V
DD
+ 0.5
Vddout + 0.5
20
50
125
UNIT
V
V
V
mA
mA
°C
°C
–0.5
–0.5
–0.5
Output voltage, V
O (2)
Input current, I
I
(V
I
< 0, V
I
> V
DD
)
Continuous output current, I
O
Junction temperature, T
J
Storage temperature, T
stg
(1)
(2)
(3)
–65
150
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in
Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
V
(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
UNIT
V
±2000
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
V
DD
V
O
V
IL
V
IH
V
I(thresh)
V
IS
V
I(CLK)
I
OH
/I
OL
C
L
T
A
f
Xtal
ESR
f
PR
C
0
/C
1
(1)
(2)
Device supply voltage
Output Yx supply voltage, Vddout
Low-level input voltage LVCMOS
High-level input voltage LVCMOS
Input voltage threshold LVCMOS
S0
Input voltage
Input voltage, CLK
Vddout = 3.3 V
Output current
Output load LVCMOS
Operating free-air temperature
Crystal input frequency (fundamental mode)
Effective series resistance
Pulling (0 V
≤
Vctrl
≤
1.8 V)
Pullability ratio
(2)
NOM
1.8
MAX
1.9
3.6
1.9
0.3 × V
DD
UNIT
V
V
V
V
V
1.7
CDCE937
CDCEL937
2.3
1.7
0.7 × V
DD
0.5 × V
DD
0
0
0
Vddout = 2.5 V
Vddout = 1.8 V
–40
8
±120
0
27
±150
V
DD
220
1.9
3.6
1.9
±12
±10
±8
10
85
32
100
S1, S2, SDA, SCL,
V
I(thresh)
= 0.5 V
DD
V
V
mA
pF
°C
MHz
Ω
ppm
V
CRYSTAL AND VCXO
(1)
Frequency control voltage, Vctrl
For more information about VCXO configuration, and crystal recommendation, see
VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in
VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
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5
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links:
CDCE937 CDCEL937
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