Low Skew, 1-to-15,
LVCMOS/LVTTL Clock Generator
Data Sheet
87974I
G
ENERAL
D
ESCRIPTION
The 87974I is a low skew, low jitter 1-to-15 LVCMOS/
LVTTL Clock Generator/Zero Delay Buffer. The device
has a fully integrated PLL and three banks whose divider
ratios can be independently controlled, providing output
frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In
addition, the external feedback connection provides for a wide
selection of output-to-input frequency ratios. The CLK0 and
CLK1 pins allow for redundant clocking on the input and dynam-
ically switching the PLL between two clock sources.
Guaranteed low jitter and output skew characteristics make
the 87974I ideal for those applications demanding well defined
performance and repeatability.
F
EATURES
•
Fully integrated PLL
•
Fifteen single ended 3.3V LVCMOS/LVTTL outputs
•
Two LVCMOS/LVTTL clock inputs for redundant clock applica-
tions
•
CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
•
Output frequency range: 8.33MHz to 125MHz
•
VCO range: 200MHz to 500MHz
•
External feedback for ”zero delay” clock regeneration
•
Cycle-to-cycle jitter: ±100ps (typical)
•
Output skew: 350ps (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free RoHS-compliant package
P
IN
A
SSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 26, 2016
87974I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 15, 19,
24, 30, 35, 39,
43, 47, 51
Name
GND
Power
Type
Description
Power supply ground.
Active HIGH outputs enabled (active). When LOW, outputs are disabled
(High-impedance state) and reset of the device. During reset/output
disable the PLL feedback loop is open and the internal VCO is tied to its
lowest frequency. The 87974I requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupt-
ed. The length of the reset pulse should be greater than one reference
clock cycle (CLKx)
Synchronizing clock enable. When HIGH, clock outputs QAx:QCx
are enabled. When LOW, clock outputs QAx:QCx are low.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
Selects divide value for Bank C output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
Selects between the PLL and the reference clock as the input to the di-
viders. When HIGH, selects PLL. When LOW, selects the reference clock.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
Reference clock input. LVCMOS / LVTTL interface levels.
No connect.
Core supply pin.
Analog supply pin.
Pulldown
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank A clock outputs.
Output supply pin for QFB clock output.
Clock output. LVCMOS / LVTTL interface levels.
Pullup
Feedback input to phase detector for generating clocks with
“zero delay”. Connect to pin 29.
LVCMOS / LVTTL interface levels.
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank B clock outputs.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank C clock outputs.
Pulldown
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
2
nMR/OE
Input
Pullup
3
4
5
6
7
8
9
10
11, 27, 42
12
13
14, 20
16, 18,
21, 23, 25
17, 22, 26
28
29
31
32, 34,
36, 38, 40
33, 37, 41
44, 46,
48, 50
45, 49
52
Pullup
Pulldown
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK0
CLK1
nc
V
DD
V
DDA
FB_SEL0, FB_
SEL1
QA4, QA3,
QA2, QA1, QA0
V
DDOA
V
DDOFB
QFB
FB_IN
QB4, QB3,
QB2, QB1, QB0
V
DDOB
QC3, QC2, QC1,
QC0
V
DDOC
VCO_SEL
Input
Input
Input
Input
Input
Input
Input
Input
Unused
Power
Power
Input
Output
Power
Power
Output
Input
Output
Power
Output
Power
Input
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Pullup
NOTE: and refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc
4
Revision E January 26, 2016
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
