JARO high voltage series Multilayer Ceramic Capacitors are constructed by depositing alternative layers of ceramic dielectric materials and internal metallic electrodes, by
using advanced ceramic manufacturing technology, and co-firing into an indestructible homogeneous body, then completed with application of metal end terminations which
are fired on to assure that permanent connection of individual internal electrodes are in parallel.
The terminations are nickel-plated and then solder plated to give the chip capacitors nickel-barrier terminations which have much better leaching resistance during soldering.
Reliable performances are built-in through exact formulation of dielectric powders, preparation of conductive paste, advanced automatic manufacturing, and strict quality
control to assure excellent control in dielectric thickness, electrode integrity, and electrode-to-termination continuity.
JARO offers the high performance MLCC of high voltage. There are five standard sizes 0805, 1206, 1210, 1808, and 1812 and ranging from 100V to 2KV in COG and X7R
characteristics.
RECOMMENDED APPLICATIONS
Modems
LAN/WAN Interface
Power Supplies
Telecom Devices
Industrial Controls
MECHANICAL DATA
Component outline:
CAPACITOR DIMENSIONS
Size
(L) Length
(W) Width
(E) Termination
mm
(in)
mm
(in)
mm
(in)
0805
2.00 ± 0.20
(.080 ± .008)
1.20 ± 0.20
(.050 ± .008)
0.50 ± 0.20
(.020 ± .008)
1206
3.20 ± 0.20
(.126 ± .008)
1.60 ± 0.20
(.063 ± .008)
0.50 ± 0.20
(.020 ± .008)
1210
3.20 ± 0.30
(.126 ± .012)
2.50 ± 0.30
(.100 ± .012)
0.50 ± 0.20
(.020 ± .008)
1808
4.50 ± 0.30
(.177 ± .012)
2.00 ± 0.20
(.080 ± .008)
0.64 ± 0.38
(.025 ± .015)
1812
4.50 ± 0.30
(.177 ± .012)
3.20 ± 0.30
(.126 ± .012)
0.64 ± 0.38
(.025 ± .015)
Dimensions are in millimeters, dimensions in parenthesis are in inches.
6600 Park of Commerce Blvd. • Boca Raton, FL 33487
Class I (COG) capacitors shall be conditioned for 96 ± 4hr by heating in a circulationg air oven at a temperature of 55 ± 2°C and a relative humidity not exceeding 20%.
The capacitor shall then be allowed to cool in a desiccator using a suitable desiccant, such as activated alumina or sillica gel, and shall be kept therein from the time of
removal from the oven to the beginning of the specified tests.
Class II (X7R, Z5U, Y5V) capacitors shall be made a special pre-conditioning before a test or a sequence of tests under the following conditions: Exposure at 150 ±
10°C for 1 hr, followed by setting the capacitor at room temperature for 24 ± 1 hr.
*2.
Capacitance is within specified tolerance; measured 1000 hours after date of manufacture because of capacitance aging of class II capacitor.
TYPICAL PERFORMANCE CURVES
6600 Park of Commerce Blvd. • Boca Raton, FL 33487
At least 75% of termination area should be well tinned.
No visible damage.
At least 75% of termination should be covered by solder.
No visible damage.
COG (1BCG)
X7R (2R1)
∆C/C
≤
± 0.5%, or ± 0.5pF
≤
+10%
whichever is greater
-5%
No visible damage.
COG (1BCG)
X7R (2R1)
∆C/C
≤
± 1%, or ± 1pF
≤
+10%
whichever is greater
D.F.
≤
1.5 x initial requirement
I.R.
≥
0.25 x initial requirement
No visible damage.
COG (1BCG)
X7R (2R1)
∆C/C
≤
± 2%, or ± 1pF
≤
+20%
whichever is greater
D.F.
≤
2.0 x initial requirement
≤
1.5 x initial requirement
I.R.
≥
0.25 x initial requirement
No visible damage.
COG (1BCG)
∆C/C
D.F.
I.R.
≤
± 2%, or ± 1pF
whichever is greater
≤
2.0 x initial requirement
Rapid Change of
Temperature
*2
IEC 384-10 4.12 /JIS C 5102 9.3
-55C to +125°C, 5 cycles (COG, X7R)
Duration: 30 mins.
Recovery: 6~24 hrs. (COG)
24 ± 2 hrs. (X7R)
IEC 384-10 4.15
1000 hrs. at maximum temperature applied
with 2.0 x U
R
(≤ 250V), 1.5 x U
R
(≤ 1KV),
1.2 x U
R
(≤ 2KV)
Recovery: 6~24 hrs. (COG)
24 ± 2 hrs. (X7R)
Endurance
(Life Test)
*3
Humidity Test
(Damp heat,
steady state)
*4
IEC 384-10 4.14 /JIS C 5102 9.5
500 hrs. at 40 ± 2°C, 90-95% RH
Recovery: 6~24 hrs. (COG)
24 ± 2 hrs. (X7R)
X7R (2R1)
≤
+10%
≤
1.5 x initial requirement
≥
0.25 x initial requirement
Adhesion
IEC 384-10 4.8 /JIS C 5102 8.11.2
Capacitors mounted on a substrate, a force of 5N
applied perpendicular to the plane of substrate and
parallel the line joining the centre of terminations
for 10 ± 1 secs.
No visible damage.
*1~4: Class II (X7R, Z5U, Y5V) capacitors shall be made a special pre-conditioning before a test or a sequence of tests under the following conditions: Exposure at 150 ±
10°C for 1 hr, followed by setting the capacitor at room temperature for 24 ± 1 hr.
6600 Park of Commerce Blvd. • Boca Raton, FL 33487
Yamaha Motor Group旗下的i-PULSE有限公司日前已与华尔莱科技(Valor)结为合作伙伴关系,基于Valor的vPlan生产规划工具向i-PULSE组装设备的使用者提供完整的从设计到制造的NPI解决方案。在近期日本东京举办的Protec展会(6/11-6/13)上,i-PULSE首度展出了该新产品并将直接向其客户进行销售。 新产品的名称为“iPlan”,它将提供一系...[详细]
2008年8月26-29日,华南地区的五大品牌工业展会——NEPCON / EMT 华南展(第十四届华南国际电子生产设备暨微电子工业展/华南国际电子制造技术展览会)、华南国际汽车电子展(AE South China)、华南国际工业组装技术与装备展览会(ATE South China)和华南国际平面显示器制造技术展(Finetech South China)将在深圳会展中心隆重举行。从组委会获...[详细]