Da ta S h e e t , V 2 .0, J a n . 2 00 1
C161K
C161O
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
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Da ta S h e e t , V 2 .0, J a n . 2 00 1
C161K
C161O
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C161K/O
Revision History:
Previous Version:
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2001-01
03.97
09.96
(Preliminary)
(Advance Information)
V2.0
Subjects (major changes since last revision)
Converted to Infineon layout
C161V removed
Ordering Codes and Cross-Reference replaced with Derivative Synopsis
Open drain functionality described for P2, P3, P6
Bidirectional reset introduced
Figure updated
Revised description of Absolute Max. Ratings and Operating Conditions
Specifications for reduced supply voltage introduced
Reduced power consumption
Clock Generation Modes added
Description of External Clock Drive improved
Standard 25-MHz timing introduced (timing granularity 2 ns)
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16-Bit Single-Chip Microcontroller
C166 Family
C161K/O
C161K/O
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16
×
16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM) on C161O,
1 KByte IRAM on C161K
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers on C161O,
one Timer Unit with 3 Timers on C161K
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 4 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Four Programmable Chip-Select Signals on C161O,
two Chip-Select Signals on C161K
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 63 General Purpose I/O Lines
• Power Supply: the C161K/O can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package (0.65 mm pitch)
Data Sheet
1
V2.0, 2001-01
嵌入式系统
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