IS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns
• Low Active Power: 50 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 32-pin sTSOP-I, 32-pin SOP and
32-pin TSOP-II packages
• Commercial, Industrial and Automotive tem-
perature ranges available
• Lead-free available
JULY 2011
4,194,304-bit static RAMs organized as 524,288 words by
8 bits. They are fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times as
fast as 45ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE. The
active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62C5128BL and IS65C5128BL are packaged in the
JEDEC standard 32-pin sTSOP-I, 32-pin SOP and 32-pin
TSOP-II packages
DESCRIPTION
The
ISSI
IS62C5128BL and IS65C5128BL are high-speed,
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
06/28/2011
1
IS62C5128BL, IS65C5128BL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O0-I/O7
High-Z
High-Z
d
out
d
in
I/O PIN
V
DD
Current
i
sb
1
, i
sb
2
i
CC
1
, i
CC
2
i
CC
1
, i
CC
2
i
CC
1
, i
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
t
stg
P
t
i
out
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
in
C
out
Parameter
Input Capacitance
Output Capacitance
Conditions
V
in
= 0V
V
out
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a
= 25°C, f = 1 MHz, V
dd
= 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
oh
V
ol
V
ih
V
il
i
li
i
lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(1)
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
= Min., i
oh
= –1.0 mA
V
dd
= Min., i
ol
= 2.1 mA
GND ≤ V
in
≤ V
dd
GND ≤ V
out
≤ V
dd
Outputs Disabled
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Min.
2.4
—
2.2
–0.3
–1
–2
–5
–1
–2
–5
Max.
—
0.4
V
dd
+ 0.5
0.8
1
2
5
1
2
5
Unit
V
V
V
V
µA
µA
Note:
1. V
ill
(min) = -2.0V AC (pulse width <10 ns). Not 100% tested.
V
ihh
(max) = V
dd
+ 2.0V AC (pulse width <10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
06/28/2011
3
IS62C5128BL, IS65C5128BL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
t
rC
t
aa
t
oha
t
aCe
t
doe
t
hzoe
(2)
t
lzoe
(2)
t
hzCe
(2)
t
lzCe
(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
-45
Min. Max.
45 —
—
3
—
—
0
5
0
5
45
—
45
20
15
—
15
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
1838
Ω
5V
OUTPUT
30 pF
Including
jig and
scope
994
Ω
5V
OUTPUT
5 pF
Including
jig and
scope
994
Ω
1838
Ω
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
06/28/2011
5
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