AN3001
Application note
Demonstration board user guidelines for the
TS4657 single supply stereo digital audio line driver
Introduction
This application note focuses on the TS4657 demonstration board, designed to evaluate
STMicroelectronics’ TS4657 device.
This document provides:
■
■
■
a brief description of the TS4657 device.
a description of the demonstration board and all of its components.
the layout of the demonstration board.
TS4657 demonstration board
Figure 1.
July 2009
Doc ID 15911 Rev 1
1/12
www.st.com
About the TS4657
AN3001
1
About the TS4657
The TS4657 is a stereo digital-to analog-converter (DAC) that integrates a high-
performance audio line driver capable of generating a 2.2 Vrms output level from a single
3.0 to 5.5 V supply.
One single supply is sufficient for the digital and analog parts of the circuit, thus eliminating
the need for external regulators.
The TS4657 is a low-power consumption device. It features only 22 mW power dissipation
at a 3.0 V power supply in full operation.
A 16-bit multi-bit sigma delta DAC is used, operating at 256xFs with oversampling digital
interpolation filters. The digital audio data can be 16- to 24-bit long and sample rates from
32 to 48 kHz are supported.
The output stage signal is ground-referenced by using an internal self-generated negative
power supply, and as such external bulky output coupling capacitors are not necessary.
The TS4657 features the following.
●
●
●
●
●
●
●
●
●
●
●
Power supply range: 3.0 V to 5.5 V.
Audio line output: 2.2 Vrms for all V
CC
range.
16- to 24-bit audio data format stereo DAC, 32 to 48 kHz sample rate.
I²S, right- or left-justified compatible digital audio interface.
95 dB SNR A-weighted at 48 kHz, V
CC
= 5 V.
Low current consumption of 7.4 mA at V
CC
= 3.0 V, full operation.
Internal negative power supply to ensure ground-referenced, capless outputs.
No necessity for an external capacitor for negative power supply generation.
Integrated structure to suppress pop and click noise
Standby mode active low.
QFN20 package, 4 mm x 4 mm,500 µm pitch.
Refer to the datasheet entitled "Single
supply stereo digital audio line driver with 2.2 Vrms
capless outputs"
for complete information on the TS4657.
2/12
Doc ID 15911 Rev 1
AN3001
Description of the demonstration board
2
Description of the demonstration board
The TS4657 demonstration board has been designed for evaluation purposes. The TS4657
device is soldered on a two-layer PCB.
Some key features of the TS4657 can be directly controlled through connectors or jumpers
on the demonstration board (Table
1).
Table 1.
Connector
J1
J2
J3
J4
J5
J6
J7
MCLK: master clock input
BCLK: bit clock input
SDAT: serial data input
LRCLK: left right clock input (channel selector input)
Power supply connector (V
CC
and GND). Power supply voltage of the TS4657 from
3.0 to 5.5 V.
Left audio output
Right audio output
Allows selection of level on Format1 pin. Format1 and Format2 pins select the digital
input format (see
section 4.1.2 Digital audio input format
in the TS4657 datasheet).
If the jumper is removed, it is possible to control the Format1 by an external logic
signal (see
section 3.3 DAC and output stage performances
in the TS4657
datasheet).
Allows selection of level on Format2 pin. Format1 and Format2 pins select the digital
input format (see
section 4.1.2 Digital audio input format
in the TS4657 datasheet).
If the jumper is removed, it is possible to control the Format2 by an external logic
signal (see
section 3.3 DAC and output stage performances
in the TS4657
datasheet).
Controls the chip standby (JP1:1-2 = circuit activated, 2-3 = circuit in standby mode).
If the jumper is removed, it is possible to control the standby by an external logic
signal (see
section 3.3 DAC and output stage performances
in the TS4657
datasheet).
Allows connection of the C6 capacitor (used for the left output filter;
see
Section 3.3: Output filters on page 6).
Allows short-circuiting of the R5 resistor (used for the left output filter; see
Section 3.3: Output filters on page 6).
Allows connection of the C7 capacitor (used for the right output filter; see
Section 3.3: Output filters on page 6).
Allows short-circuiting of the R7 resistor (used for the right output filter; see
Section 3.3: Output filters on page 6).
Demonstration board connectors
Description
JP1
JP2
JP3
JP4
JP5
JP6
JP7
Caution:
When you apply the power supply through J5, do not invert the polarity as doing so will
damage the chip.
Doc ID 15911 Rev 1
3/12
Description of the demonstration board
Figure 2.
Schematic diagram
VCCD VCCA
C2
1uF
C3
1uF
C4
1uF
C5
1uF
AN3001
3v
to 5V5
VCC
GND
J5
VCCA VCCD
10
uF/6V3
C1
13
19
18
2
20
14
IC1
VREGD
VCCD
VREGA
nc
nc
VCCA
C6
2nF2
JP4
R6
nc
3
LRCLK
J4
820
R5
J6
SIP2
LRCLK
SDAT
BCLK
MCLK
4
Digital
input
SDAT
J3
5
BCLK
MCLK J1
100K
R1
100K
R2
100K
R3
100K
R4
J2
Digital
audio
interface
6
Digital
filters
and
DACs
VOUTL
12
JP5
OUT L
VOUTR
11
R7
820
JP7
OUT R
R8
nc
JP6
C7
2nF2
J7
SIL2
Control
interface
FORMAT1
FORMAT2
TS4657
/STDBY
GNDD
GNDD
GNDA
GNDA
GNDA
Output filters
Epad
VCCD
1
2
3
1
2
3
1
2
3
JP1
JP2
JP3
Format1 Format2
/Stdby
User control
1
17
10
15
16
8
7
9
AM04525
Table 2.
Component list for the demonstration board
Quantity
1
4
2
4
2
2
11
3
1
Description
10 µF/6.3 V +/-20 %, SMD electrochemical capacitor
1 µF/10 V X5R, +/-10 %, SMD ceramic capacitors 0603
2.2 nF/50 V X7R, +/-10 %, SMD ceramic capacitors 0603
100 K/1 %, 0.063 W, SMD resistors, 0603
820 ohms/1 %, 0.063 W, SMD resistors, 0603
Not connected (see
Section 3.4: Optional measurement loads on page 7)
2-pin header 2.54 mm pitch
3-pin header 2.54 mm pitch
TS4657IQT
Name
C1
C2, C3, C4, C5
C6,C7
R1, R2, R3, R4
R5, R7
R6, R8
J1, J2, J3, J4, J5,
J6, J7,
JP4, JP5, JP6, JP7
JP1, JP2, JP3
IC1
4/12
Doc ID 15911 Rev 1
AN3001
Configuring the demonstration board
3
3.1
Configuring the demonstration board
Serial data input configuration
The TS4657 receives serial digital audio data through a 3-wire interface. SDAT is the serial
audio data input. The data is entered MSB first and is a two’s complement. The data can be
I
2
S, right- or left-justified. The data format is chosen with the control pins FORMAT1 and
FORMAT2 as detailed in
Table 3.
The level on both of these pins should be fixed before waking-up the chip.
Table 3.
FORMAT2
Digital audio data formats supported by the TS4657
BCLK/LRCLK ratio
FORMAT1
Data Format
Min
Max
256
256
256
256
Right-justified, 16-bit data
Data valid on rising edge of BCLK
Right-justified, 24-bit data
Data valid on rising edge of BCLK
Left-Justified, 16-bit up to 24-bit data
Data valid on rising edge of BCLK
I²S, 16-bit up to 24-bit data
Data valid on rising edge of BCLK
0
0
1
1
0
1
0
1
32
48
2 x number of bits of data
2 x number of bits of data
3.2
Sample rate capability
Three external clock signals are applied to the TS4657. The MCLK is the external master
clock applied by the audio data processor. The LRCLK is the channel frequency, also called
LEFT/RIGHT clock, at which the digital words for each channel are input to the device. The
LRCLK clock is the sample rate of the audio data. The ratio MCLK/LRCLK must be an
integer, as shown in
Table 4.
The BCLK is the bit clock and represents the clock at which the audio data is serially shifted
into the audio port. BCLK is linked to LRCLK. The minimum required BCLK frequency is
twice the audio sample rate multiplied by the number of bits in each audio word. Refer to
Table 3
for the BCLK/LRCLK ratio. MCLK, LRCLK and BCLK must be synchronous clock
signals.
Table 4.
Audio data sampling rates
MCLK (MHz)
LRCLK (kHz)
256x
32
44.1
48
8.192
11.2896
12.288
Doc ID 15911 Rev 1
5/12
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