MYSON
TECHNOLOGY
MTV312M64
(Rev 0.99)
8051 Embedded Monitor Controller
Flash Type with ISP
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 12MHz operating frequency with double CPU clock option
0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating
1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)
Maximum 14 channels of PWM DAC
Maximum 31 I/O pins
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
Built-in low power reset circuit
Built-in self-test pattern generator with four free-running timings
Compliant with VESA DDC1/2B/2Bi/2B+ standard
Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
Single master IIC interface for internal device communication
Maximum 4-channel 6-bit ADC
Watchdog timer with programmable interval
Flash-ROM program code protection selection
40-pin DIP, 42-pin SDIP or 44-pin PLCC package
GENERAL DESCRIPTIONS
The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC
interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P3.0-2
P3.4-5
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P0.0-7
P2.0-3
RD
WR
ALE
INT1
XFR
AUXRAM &
DDCRAM
8051
CORE
RST
X1
X2
AD0-3
ADC
H/VSYNC
CONTROL
HSYNC
VSYNC
HBLANK
VBLANK
ISCL
ISDA
HSCL
HSDA
PWM DAC
P6.0-7
P5.0-6
P4.0-2
AUX
I/O
DA0-13
DDC & IIC
INTERFACE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.99
-1-
2001/07/26
MYSON
TECHNOLOGY
PIN CONNECTION
MTV312M64
(Rev 0.99)
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD3
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MTV312M
40 Pin
PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HLFHO
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
RST
P6.6/DA12
P6.5/DA11
P6.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P6.0/AD0
P6.1/AD1
P1.7
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD3
NC
NC
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTV312M
42 Pin
SDIP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HLFHO
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P6.6/DA12
P6.5/DA11
P6.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P6.0/AD0
P6.1/AD1
P1.7
P1.6
P1.5
DA0/P5.0
VDD3
NC
NC
RST
VDD
P6.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
7
8
9
10
11
12
13
14
15
16
17
MTV312M
44 Pin
PLCC
DA2/P5.2
DA1/P5.1
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC
39
38
37
36
35
34
33
32
31
30
29
DA8/HLFHO
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P6.7/DA13
P6.6/DA12
P6.5/DA11
P6.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P6.0/AD0
P6.1/AD1
P1.7
P1.6
40
41
42
43
44
1
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
P1.5
P1.4
P1.3
P1.2
P3.2/INT0
P1.1
Revision 0.99
-2-
2001/07/26
MYSON
TECHNOLOGY
PIN CONFIGURATION
MTV312M64
(Rev 0.99)
A “CMOS output pin” means it can sink and drive at least 4mA current. It is not recommended to use such
pin as input function.
A “open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as
input or output function and needs an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA
to maintain the pin at high level. It can be used as input or output function. It needs an external pull up
resistor when driving heavy load device.
4mA
10uA
120uA
2 OSC
period
delay
4mA
Output
Data
Input
Data
8051 Standard Pin
Pin
4mA
No Current
Output
Data
4mA
Pin
Input
Data
4mA
Output
Data
Pin
CMOS Output Pin
Open Drain Pin
POWER CONFIGURATION
The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all
output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V.
However, X1 and X2 pins must be kept below 3.3V.
In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,
HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And
the ADC conversion range is 3.3V.
5V
VDD
VDD3
10u
3.3V
VDD
VDD3
MTV312M in
5V System
MTV312M in
3.3V System
Revision 0.99
-3-
2001/07/26
MYSON
TECHNOLOGY
PIN DESCRIPTION
Name
VDD3
VDD
VSS
X2
X1
RST
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/HCLAMP
DA8/HLFHO
DA9/HALFV
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P3.2/INT0
ISDA/P3.4/T0
ISCL/P3.5/T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P6.0/AD0
P6.1/AD1
P6.2/AD2/HLFHI
P6.3/AD3
P6.4/DA10
P6.5/DA11
P6.6/DA12
P6.7/DA13
VBLANK/P4.0
HBLANK/P4.1
STOUT/P4.2
HSYNC
VSYNC
PIN NO.
40 42 44
4
4
4
5
8
8
6
9
10
7
10 11
8
11 12
29
7
7
3
3
3
2
2
2
1
1
1
38 40 42
37 39 41
36 38 40
30 32 34
31 33 35
35 37 39
34 36 38
25 28 29
24 27 28
15 18 19
9
12 13
10 13 14
13 16 17
14 17 18
16 19 20
17 20 21
18 21 22
19 22 23
20 23 24
21 24 25
23 26 27
22 25 26
12 15 16
-
-
9
26 29 30
27 30 31
28 31 32
-
-
33
32 34 36
33 35 37
11 14 15
39 41 43
40 42 44
Type
O
-
-
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
Description
MTV312M64
(Rev 0.99)
3.3V core power
5V or 3.3V Positive Power Supply
Ground
Oscillator output
Oscillator input
Active high reset
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / General purpose I/O (CMOS)
PWM DAC output / Hsync clamp pulse output (CMOS)
PWM DAC output / Hsync half freq. Output (open drain)
PWM DAC output / Vsync half freq. Output (open drain)
Slave IIC clock / General purpose I/O / Rxd (open drain)
Slave IIC data / General purpose I/O / Txd (open drain)
General purpose I/O / INT0 (8051 standard)
Master IIC data / General purpose I/O / T0 (open drain)
Master IIC clock / General purpose I/O / T1 (open drain)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O (CMOS output or 8051 standard)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input / Half Hsync input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / PWM DAC output (CMOS)
General purpose I/O / PWM DAC output (CMOS)
General purpose I/O / PWM DAC output (CMOS)
General purpose I/O / PWM DAC output (CMOS)
Vertical blank (CMOS) / General purpose Output (CMOS)
Horizontal blank (CMOS) / General purpose Output (CMOS)
Self-test video output (CMOS) / General purpose Output (CMOS)
Horizontal SYNC or Composite SYNC Input
Vertical SYNC input
Revision 0.99
-4-
2001/07/26
MYSON
TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV312M64
(Rev 0.99)
The CPU core of MTV312M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core
fetches its program code from the 64K bytes Flash in MTV312M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz
X’ is applied on MTV312M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency.
tal
Note: All registers listed in this document reside in 8051’ external RAM area (XFR). For internal RAM
s
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV312M, the same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 512 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 9FFh. Programs
can use "MOVX" instruction to access the AUXRAM.
2.5 Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can
use "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC02
EEPROM is connected onto the interface.
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
SFR
Accessible by
direct addressing
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
EFFh
DDCRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
80h
7Fh
F00h
Internal RAM
Accessible by
direct and indirect
addressing
E00h
9FFh
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
00h
800h
Revision 0.99
-5-
2001/07/26
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