8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,
high performance CMOS SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches. The SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power
supply. These devices conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 512K x16
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST39VF801C/802C
– 3.0-3.6V for SST39LF801C/802C
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns for SST39VF801C/802C
– 55 ns for SST39LF801C/802C
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• Sector-Erase Capability
– Uniform 2 KWord sectors
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one 16-, and
fifteen 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25041A
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Product Description
The SST39VF801C/802C and SST39LF801C/802C devices are 512K x16 CMOS Multi-Purpose Flash
Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF801C/802C and SST39LF801C/802C write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high performance Word-Program, the SST39VF801C/802C and SST39LF801C/802C
devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,
or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent
write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39VF801C/802C and SST39LF801C/802C devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system appli-
cations, they significantly improve performance and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less current to program and has a shorter erase
time, the total energy consumed during any Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while lowering the cost for program, data, and con-
figuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF801C/802C and SST39LF801C/802C
are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4
for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
2
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Block Diagrams
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
RY/BY#
I/O Buffers and Data Latches
Control Logic
DQ
15
- DQ
0
1434 B1.0
Figure 1:
Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
3
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Pin Assignment
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Standard Pinout
Top View
Die Up
1434 48-tsop EK P1.0
Figure 2:
Pin Assignments for 48-Lead TSOP
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A9
A8
A10
NC
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
NC DQ5 DQ12 VDD DQ4
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE# VSS
WE# RST#
RY/BY# WP# A18
A7
A3
A17
A4
A6
A2
A
B
C
D
E
F
G
H
1434 48-tfbga B3K P2.0
Figure 3:
Pin Assignments for 48-Ball TFBGA
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
4
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
TOP VIEW (balls facing down)
6
5
4
3
2
1
A2
A1
A0
A4
A3
A5
A6
A7
A18
A17
WP#
NC
NC
WE# RST# A9
RY/BY# A10
A8
A11
A13
A12
A14
A15
CE# DQ8 DQ10
VSS OE# DQ9
NC
NC
DQ4 DQ11 A16
DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
A B C D E F G H J K L
1434 48-wfbga MAQ P3.0
Figure 4:
Pin Assignments for 48-Ball WFBGA
Table 1:
Pin Description
Symbol
A
MS1
-A
0
Pin Name
Address Inputs
Functions
To provide memory addresses.
During Sector-Erase A
MS
-A
11
address lines will select the sector.
During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Write Protect
Reset
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Ready/Busy#
Unconnected pins.
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25041
WP#
RST#
CE#
OE#
WE#
V
DD
V
SS
NC
RY/BY#
To protect the top/bottom boot block from Erase/Program operation when
grounded.
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
1. A
MS
= Most significant address
A
MS
= A
18
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
5
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