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CA91C078A-40CG: 产品描述VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小3MB，共350页; 制造商Silicon360

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CA91C078A-40CG概述

VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299

CA91C078A-40CG规格参数

参数名称	属性值
厂商名称	Silicon360
零件包装代码	PGA
包装说明	PGA,
针数	299
Reach Compliance Code	unknown
地址总线宽度	32
最大时钟频率	40 MHz
最大数据传输速率	50 MBps
驱动器接口标准	IEEE 1149.1
外部数据总线宽度	32
JESD-30 代码	S-CPGA-P299
长度	52.324 mm
端子数量	299
最高工作温度	70 °C
最低工作温度
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	PGA
封装形状	SQUARE
封装形式	GRID ARRAY
座面最大高度	5.0546 mm
最大供电电压	5.25 V
最小供电电压	4.25 V
标称供电电压	5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	PIN/PEG
端子节距	5.08 mm
端子位置	PERPENDICULAR
宽度	52.324 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, VME

文档解析

SCV64™ 在中断处理和系统控制方面提供全面解决方案。芯片集成 VMEbus 中断器和中断处理器，支持七级中断（IRQ1*-IRQ7*），可配置为自动向量或向量模式，并处理本地中断映射。中断状态和使能寄存器允许软件监控中断源，而中断应答周期（IACK）通过本地或 VMEbus 路径高效响应。系统控制器功能包括自动系统控制器检测、IACK 菊花链驱动和 VMEbus 仲裁器，后者支持多种仲裁模式（如优先级和轮询）和超时保护，确保多主系统公平访问总线。数据路径管理结合 FIFO 和 DMA，优化中断驱动传输。DMA 控制器支持填充选项和传输错误检查，可处理大块数据中断响应。位置监控器通过 LMINT 中断实现事件通知，LMFIFO 提供深度缓冲。BI-Mode 增强系统健壮性，允许在中断风暴或故障时隔离板卡。本地总线接口包含定时器模块（如滴答定时器和总线超时定时器），辅助实时调度。应用上，该芯片适合高中断负载环境，如数据采集系统或网络设备。其解耦数据路径减少中断延迟，而 VMEbus 系统控制功能简化背板管理。初始化过程支持自动 SYSCON 选择和基址配置，降低开发复杂度。整体设计符合 VME64 规范，确保兼容性和可扩展性。

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SCV64™ User Manual

http://www.silicon360.com

Table of Contents

General Information ............................................................................................ 1-1

1.1

1.2

1.3

1.4

Introduction............................................................................................. 1-1

Product Overview ................................................................................... 1-1

1.2.1

Flexibility and Features.......................................................... 1-1

Using This Document ............................................................................. 1-4

Conventions ............................................................................................ 1-5

1.4.1

1.4.2

1.4.3

Signals .................................................................................... 1-5

Symbols.................................................................................. 1-5

Mathematical Notation........................................................... 1-5

Functional Description......................................................................................... 2-1

2.1

Introduction............................................................................................. 2-1

2.1.1

2.1.2

2.1.2.1

2.1.2.2

2.1.2.3

2.2

2.2.1

2.2.2

2.2.2.1

2.2.2.2

2.2.3

2.2.3.1

2.2.3.2

2.2.3.3

2.2.4

2.2.4.1

2.2.4.2

Organization of the Functional Description........................... 2-1

Functional Overview.............................................................. 2-2

Data Path ............................................................................... 2-2

VMEbus Interface ................................................................. 2-5

Local Bus Interface ............................................................... 2-6

Function.................................................................................. 2-8

Bus Request Modes................................................................ 2-9

Fair and Demand Modes ....................................................... 2-9

VMEbus Request Levels....................................................... 2-9

Bus Release Modes .............................................................. 2-10

Bus Clear Enabling ............................................................. 2-10

Release On Request and Release When Done .................... 2-10

Ownership Timer ................................................................ 2-11

Other Bus Release Mechanisms........................................... 2-11

Local Memory Interrupt ...................................................... 2-11

BI-Mode .............................................................................. 2-12

VMEbus Requester ................................................................................. 2-8

iii

2.2.4.3

2.3

2.3.1

2.3.1.1

2.3.1.2

2.3.1.3

2.3.2

2.4

2.4.1

2.4.1.1

2.4.2

2.4.2.1

2.4.2.2

2.4.2.3

2.4.2.4

2.5

2.5.1

2.5.2

2.5.3

2.5.3.1

2.5.3.2

2.5.3.3

2.5.4

2.5.5

2.5.6

2.5.6.1

2.5.6.2

2.5.7

2.6

2.6.1

2.6.1.1

Local and System Reset ....................................................... 2-12

VMEbus Interrupts ...............................................................2-13

Interrupt Generation............................................................. 2-13

BI-mode Effects ................................................................... 2-14

Reset Effects ........................................................................ 2-14

Local Bus Interrupts..............................................................2-15

Interrupt Enabling and Status ...............................................2-20

Local Interrupt Level Mapping............................................ 2-21

Interrupt Acknowledge Cycles .............................................2-22

Auto-Vectored Interrupts ..................................................... 2-25

Vectored Interrupts .............................................................. 2-26

BI-Mode Effects .................................................................. 2-29

Reset Effects ........................................................................ 2-29

Syscon Determination...........................................................2-30

IACK Daisy Chain Driver ....................................................2-31

VMEbus Arbiter ...................................................................2-31

Arbitration Modes............................................................... 2-31

Arbitration Time-out............................................................ 2-33

Reset Effects ........................................................................ 2-33

Bus Timer .............................................................................2-34

System Clock Driver.............................................................2-34

External Inputs ......................................................................2-34

External Status ..................................................................... 2-34

Off-Board Reset Input ......................................................... 2-35

Reset Effects on Syscon Functions .......................................2-35

SCV64 as VME Slave...........................................................2-39

Coupled Mode...................................................................... 2-39

Interrupter .............................................................................................. 2-13

Interrupt Handler ................................................................................... 2-18

System Controller Functions ................................................................. 2-30

Data Path................................................................................................ 2-36

2.6.1.2

2.6.2

2.6.2.1

2.6.2.2

2.6.2.3

2.7

2.7.1

2.7.2

2.7.2.1

2.7.2.2

2.8

2.8.1

2.8.1.1

2.8.1.2

2.8.1.3

2.8.1.4

2.8.1.5

2.8.2

2.8.2.1

2.8.2.2

2.8.2.3

2.8.3

2.8.4

2.8.5

2.8.6

2.8.7

2.8.8

2.9

2.9.1

2.9.1.1

2.9.1.2

Decoupled Mode ................................................................. 2-39

SCV64 as VME Master........................................................ 2-41

Coupled Mode..................................................................... 2-41

Decoupled Mode ................................................................. 2-42

DMA Transfers ................................................................... 2-43

CPU Memory Map............................................................... 2-45

VME Slave Memory Map.................................................... 2-49

Automatic Base Address Programming .............................. 2-51

Access Protection ................................................................ 2-52

SCV64 as VME Master........................................................ 2-53

Address Translation ............................................................ 2-53

Byte Lane Translation ......................................................... 2-54

VMEbus Mastership............................................................ 2-56

RMW Cycles....................................................................... 2-57

Termination of a Master Cycle with RETRY* ................... 2-58

SCV64 as VME Slave.......................................................... 2-58

Address Translation ............................................................ 2-58

Byte Lane Translation ......................................................... 2-59

Local Bus Mastership.......................................................... 2-60

DMA Transfers .................................................................... 2-61

Master/Slave Deadlock Resolution ...................................... 2-61

Location Monitor Access ..................................................... 2-62

Bus Busy Glitch ................................................................... 2-63

BI-Mode Effects................................................................... 2-63

Bus Error Handling .............................................................. 2-64

Local Bus Arbitration........................................................... 2-66

Local Arbiter Bypassed....................................................... 2-66

Local Arbiter Active ........................................................... 2-67

Memory Mapping ................................................................................. 2-45

VMEbus Interface ................................................................................. 2-53

Local Bus Interface ............................................................................... 2-66

CA91C078A-40CG相似产品对比

	CA91C078A-40CG	CA91C078A-25EG	CA91C078A-40CQ	CA91C078A-33CQ	CA91C078A-33EG	CA91C078A-33CG	CA91C078A-33IQ	CA91C078A-25IQ
描述	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS
包装说明	PGA,	PGA,	FQFP,	FQFP,	PGA,	PGA,	FQFP,	,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
uPs/uCs/外围集成电路类型	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME
厂商名称	Silicon360	-	-	Silicon360	Silicon360	Silicon360	Silicon360	Silicon360
零件包装代码	PGA	PGA	QFP	QFP	PGA	PGA	QFP	-
针数	299	299	304	304	299	299	304	-
地址总线宽度	32	32	32	32	32	32	32	-
最大时钟频率	40 MHz	25 MHz	40 MHz	33 MHz	33 MHz	33 MHz	33 MHz	-
最大数据传输速率	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	-
驱动器接口标准	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	-
外部数据总线宽度	32	32	32	32	32	32	32	-
JESD-30 代码	S-CPGA-P299	S-CPGA-P299	S-PQFP-G304	S-PQFP-G304	S-CPGA-P299	S-CPGA-P299	S-PQFP-G304	-
长度	52.324 mm	52.324 mm	40 mm	40 mm	52.324 mm	52.324 mm	40 mm	-
端子数量	299	299	304	304	299	299	304	-
最高工作温度	70 °C	125 °C	70 °C	70 °C	125 °C	70 °C	85 °C	-
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	-
封装代码	PGA	PGA	FQFP	FQFP	PGA	PGA	FQFP	-
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-
封装形式	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH	-
座面最大高度	5.0546 mm	5.0546 mm	4.5 mm	4.5 mm	5.0546 mm	5.0546 mm	4.5 mm	-
最大供电电压	5.25 V	5.5 V	5.25 V	5.25 V	5.5 V	5.25 V	-	-
最小供电电压	4.25 V	4.5 V	4.25 V	4.25 V	4.5 V	4.25 V	-	-
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V	-
表面贴装	NO	NO	YES	YES	NO	NO	YES	-
温度等级	COMMERCIAL	MILITARY	COMMERCIAL	COMMERCIAL	MILITARY	COMMERCIAL	INDUSTRIAL	-
端子形式	PIN/PEG	PIN/PEG	GULL WING	GULL WING	PIN/PEG	PIN/PEG	GULL WING	-
端子节距	5.08 mm	5.08 mm	0.5 mm	0.5 mm	5.08 mm	5.08 mm	0.5 mm	-
端子位置	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	PERPENDICULAR	PERPENDICULAR	QUAD	-
宽度	52.324 mm	52.324 mm	40 mm	40 mm	52.324 mm	52.324 mm	40 mm	-

CA91C078A-40CG

CA91C078A-40CG概述

CA91C078A-40CG规格参数

文档解析

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CA91C078A-40CG相似产品对比

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