NCP1336A/B
Quasi-Resonant Current
Mode Controller for High
Power Universal Off-Line
Supplies
The NCP1336 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a novel
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This
results in a stable operation despite switching events always occurring
in the drain−source valley. This system works down to the 4
th
valley
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance.
The controller takes benefit of a high−voltage start−up current
source to provide a quick and lossless power−on sequence. To improve
the safety in overload situations, the controller includes an Over Power
Protection circuit which clamps the delivered power at high−line.
Safety−wise, an adjustable timer relies on the feedback voltage to
detect a fault. On version B, this fault triggers a triple−hiccup on the
VCC pin which naturally reduces the average input power drawn by
the converter. On version A, when a fault is detected, the controller is
latched−off.
Particularly well suited for adapter applications, the controller
features two latch inputs: one dedicated to Over Temperature
protection (OTP) which offers an easy means to connect a pull−down
temperature sensor like an NTC, and a second one more classical that
can be used to perform an accurate Over Voltage Protection.
Finally, a brownout pin which stops the circuit operation in presence
of a low mains condition is included.
Features
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QUASI−RESONANT PWM
CONTROLLER FOR HIGH POWER
AC−DC WALL ADAPTERS
MARKING
DIAGRAM
14
1
SO−14
CASE 751AN
SUFFIX O
A
x
WL
Y
WW
G
14
NCP1336xG
AWLYWW
1
= Assembly Location
= A or B
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
OPP
OTP
Timer
ZCD
Ct
FB
CS
(Top View)
HV
OVP
BO
VCC
DRV
GND
•
Quasi−Resonant Peak Current−Mode Control Operation
•
Valley Switching Operation with Valley−Lockout for Noise−Immune
•
•
•
•
•
•
•
•
•
•
•
Operation
ORDERING INFORMATION
Internal 5 ms Soft−Start
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
Loss−Free Adjustable Over Power Protection
Auto−Recovery or Latched Internal Output Short− Circuit Protection
Adjustable Timer for Improved Short−Circuit Protection
Overvoltage and Overtemperature Protection Inputs
Brownout Input
•
SO14 Package
−500 mA/+800 mA Peak Current Source/Sink
•
These are Pb−Free Devices
Capability
•
This Device uses Halogen−Free Molding Compound
Internal Temperature Shutdown
Typical Applications
Direct Optocoupler Connection
•
High Power ac−dc Converters for TVs, Set−Top Boxes etc
3
ms
Blanking Delay to Ignore Leakage Ringing at
•
Offline Adapters for Notebooks
Turn−Off
Extremely Low No−Load and Standby Power
©
Semiconductor Components Industries, LLC, 2017
1
March, 2017 − Rev. 4
Publication Order Number:
NCP1336/D
NCP1336A/B
PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
OPP
Function
Adjust the Over Power
Protection
Over−Temperature
Protection
Timer
Zero Crossing Detection
Timing Capacitor
Feedback Pin
Current Sense
−
Driver Output
Supplies the Controller
Brownout
Over−Voltage Protection
−
High−Voltage Input
Pin Description
A negative voltage applied to this pin reduces the internal maximum peak
current setpoint. Connecting it to an auxiliary winding through a resistor
divider thus performs Over Power compensation. If grounded, OPP is null.
Connect an NTC between this pin and GND pin. Pin 2 features an internal
current source that biases the NTC. When the NTC pulls the pin down, the
circuit permanently latches−off.
Wiring a capacitor to ground helps selecting the timer duration.
Connected to the auxiliary winding, this pin detects the core reset event.
A capacitor connected to this pin acts as the timing capacitor in foldback
mode.
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current.
This pin is the controller ground.
This pin is the driver’s output to an external MOSFET.
This pin is connected to an external auxiliary voltage.
This pin is the brownout input.
By pulling this pin high, the controller can be permanently latched−off.
This pin is omitted for improved creepage.
Connected to the bulk capacitor, this pin powers the internal current source
to deliver a startup current.
2
OTP
3
4
5
6
7
8
9
10
11
12
13
14
Timer
ZCD
Ct
FB
CS
GND
DRV
VCC
BO
OVP
NC
HV
OVERCURRENT PROTECTION ON NCP1336 VERSIONS
Auto−Recovery
Overcurrent protection
NCP1336 / A
NCP1336 / B
X
Latched
Overcurrent protection
X
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2
NCP1336A/B
HV−bulk
+
Vout
OPP
1
2
OTP
ZCD
3
4
5
6
7
14
13
12
11
10
9
8
BO
OVP
GND
+
Vin
NCP1336
+
GND
Figure 1. Typical Application Example
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3
NCP1336A/B
VDD
+
−
1st
HV
+
−
Rpullup
FB
+
−
HV
Startup
+
−
PNOK
VCO
Latch
V
CC
Management
VCC
+
4th
VDD
LOVP reset
Aux
3rd
TSD
2nd
HV
VDD
ICt
Ct
+
Ct
Setpoint
−
Fault
BO Reset
1 2 34
Decimal Counter
CLK rst
R
Q
Q
Ct
Discharge
+
−
Demag
A & C:
Latched
S
+
−
DRV
Grand
Reset
Grand
Reset
Clamp
DRV
Gate
Vdd
ItimerC
Timer
ItimerD
ZCD
Laux
10 V
ESD
DRV
Vth
leakage blanking
S
GND
VDD
5us Timeout
/4
+
−
Q
Q
IpFlag
S
Q
Q
PWMReset
Grand
Reset
noise delay
R
VOVP
−
VCC
R
OVP
Ipeak_min = 25% Limit
100 ns
CS
Rsense
Leading
Edge
Blanking
+
−
IpFlag
Ilimit
+ Vopp
OPP
+
Ilimit
Soft−Start
+
−
BO Reset
Noise Delay
+
−
+
−
SS End
PWM Reset
−
Soft−Start End ? Then 1 Else 0
SS End
Figure 2. Internal Circuit Architecture
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4
+
VDD
OTP
IOTP
T°
VOTP
HV
VBO
BO
+
IBO
NCP1336A/B
MAXIMUM RATINGS TABLE
Symbol
V
CCmax
I
CCmax
V
HVmax
I
HVmax
V
max
I
max
V
ZDC,dc
I
ZDC,dc
V
ZDC,pulse
I
ZDC,pulse
V
OPPmax
I
OPPneg
V
DRV(MAX)
R
qJA
TJ
MAX
Rating
Maximum Power Supply voltage, V
CC
pin, continuous voltage
Maximum current for VCC Pin
High voltage pin (pin 14) voltage range
Pin 14 current range
Maximum voltage on low power pins (except pin 4, pin 9, pin 10 and pin 14)
Current range for low power pins (except pin 4, pin 9, pin 10 and pin 14)
Maximum continuous voltage on pin 4
Maximum continuous current on pin 4
Maximum positive pulsed voltage (pulse duration below 100
ms)
on pin 4
Maximum positive pulsed current (pulse duration below 100
ms)
on pin 4
Recommended maximum operating voltage on pin OPP (pin 1)
Maximum negative current into OPP pin (pin 1)
Maximum DRV pin voltage when DRV is in High state
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, HBM model (All pins except HV) (Note 1)
ESD Capability, Machine Model (All pins except DRV) (Note 1)
ESD Capability, Machine Model (DRV pin) (Note 1)
Value
−0.3 to 28
$30
−0.3 to 500
$20
−0.3 to 10
$10
−0.3 to 10
$10
+12
+3
−300
2
V
CC
+ 1.0
120
150
−60 to +150
2
200
160
Unit
V
mA
V
mA
V
mA
V
mA
V
mA
mV
mA
V
°C/W
°C
°C
kV
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection rated using the following tests: Human Body Model 2000 V per JEDEC standard JESD22, Method
A114E. Machine Model Method 200 V per JEDEC standard JESD22, Method A115A.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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