NCP5230
Precise Low Voltage
Synchronous Buck
Controller with Power
Saving Mode
The NCP5230 is a simple single phase solution with differential
phase current sensing, power saving operation, and gate drivers to
provide accurately regulated power.
The adaptive non overlap gate drive and power saving operation
circuit provide a low switching loss and high efficiency solution for
server, notebook, and desktop systems. A high performance
operational error amplifier is provided to simplify compensation of the
system. The NCP5230 features also include soft−start sequence,
accurate overvoltage and over current protection, UVLO for VCC and
VCCP, and thermal shutdown.
Features
http://onsemi.com
MARKING
DIAGRAMS
QFN16
CASE 485G
5230
ALYWG
G
1
5230
A
L
Y
W
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Performance Operational Error Amplifier
Internal Soft−Start/Stop
±0.5%
Internal Voltage Accuracy, 0.8 V voltage reference
OCP accuracy, Four Re−entry Times Before Latch
“Lossless” Differential Inductor Current Sensing
Internal High Precision Current Sensing Amplifier
Oscillator Frequency Range of 100 kHz
−
1000 kHz
20 ns Adaptive FET Non−overlap Time of Internal Gate Driver
5.0 V to 12 V Operation
Support 1.5 V to 19 V V
in
V
out
from 0.8 V to 3.3 V (5 V with 12 V
CC
)
Chip Enable through OSC pin
Latched Over Voltage Protection (OVP)
Internally Fixed OCP Threshold
Guaranteed Startup Into Pre−Charged Loads
Thermally Compensated Current Monitoring
Thermal Shutdown Protection
Integrated MOSFET Drivers
Integrated BOOST Diode with internal R
bst
= 2.2
W
Automatic Power Saving Mode to Maximize Efficiency During Light
Load Operation
•
Sync Function
•
Remote Ground Sensing
•
This is a Pb−Free Device*
Applications
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
PIN CONNECTIONS
ROSC/EN
14
GND
VCC
16
15
13
12
11
10
9
VCCP
LG
LX
BOOT
CSP
1
2
3
4
5
6
7
8
CSN/VO
FBG
VSEN
FB
PGOOD
UG
SYNC
(Top View)
ORDERING INFORMATION
Device
NCP5230MNTWG
Package
Shipping
•
Desktop and Server Systems
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
QFN16 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
January, 2013
−
Rev. 1
1
Publication Order Number:
NCP5230/D
COMP
NCP5230
VCC
PGOOD
6
15
2.2
W
4
CSP 13
+
−
CSN/VO 12
Current Sense
Amplifier
3
UVP
OSC
LX
CDIFF
Over Current
Detector
5
BOOT
UG
−
COMP 8
FBG 11
0.8V
FB 9
VREF*125%
VREF*75%
+
−
Error Amplifier
+
−
+
Control Logic,
Protection,
RAMP
Generator and
PWM Logic
UVLO
Control
1
VCCP
OVP
2
VSEN 10
ROSC/EN 14
SYNC 7
1.24V
Programmable
OSC
VREF*50%
−
+
OVP,
UNLATCHED
LG
16 GND
Figure 1. NCP5230 BLOCK DIAGRAM
PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VCCP
LG
LX
BOOT
UG
PGOOD
SYNC
COMP
FB
VSEN
FBG
CSN/VO
CSP
ROSC/EN
VCC
GND
THERMAL PAD
Description
Power supply for bottom gate MOSFET drivers
Bottom gate MOSFET driver pin
Switch node
Supply rail for the floating top gate driver
Top gate MOSFET driver pin
Power Good. It is an open−drain output, set free after SS (with 3x clock delay) as long as the output
voltage monitored through VSEN is within specifications.
Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to
this pin. Short to GND if not used.
Output of the error amplifier
Inverting input to the error amplifier
Output Voltage Sense
Remote Ground Sense
Inductor differential sense inverting input
Inductor differential sense non−inverting input
Programs the switching frequency; EN: Pull−low to disable the device
Supply rail for the controller internal circuitry
Ground reference
Connects with the silicon substrate for good thermal contact with the PCB. Connect to GND plane.
http://onsemi.com
2
NCP5230
PGOOD
VCC
VCCP
VIN
SYNC
15
RSEN1
RS1
CSEN1
RS2
RNTC1
6
7
13
12
11
RFB2
CFB2
9
8
RF1
RFB3
RVFB1
CF1
CH1
1
4
CBOOT1
5
3
2
ROSC1
LOUT1
Q3
1
2
3
VCCP
BOOT
PGOOD
SYNC
CSP
NCP5230
CSN/VO
FBG
FB
ROSC/EN
COMP
VSEN
GND
UG
LX
LG
VCC
VOUT
3
Q4
1
+ COUT1
2
10
16
ENABLE
2
R2
R1
14
JP3
1
ETCH
Figure 2. Typical Application Circuit
ABSOLUTE MAXIMUM RATINGS
Rating
Controller Power Supply Voltages to GND
Boost Supply Voltage Input
Symbol
VCC, VCCP
BOOT
V
MAX
15
35V wrt/GND
40 V <100 ns
wrt/GND
15 wrt/LX
35
40 V
≤
50 ns
wrt/GND
15 wrt/LX
35
40 < 100 ns
15
6
PGOOD
SYNC
CSP, CSN/VO with
V
CC
= 12 V
7
7
10
V
MIN
−0.3
−0.3
Unit
V
V
High−Side Driver Output
(Top Gate)
UG
−0.3
wrt/LX
−5
V < 200 ns
V
Switching Node
(Bootstrap Supply Return)
Low−Side Driver Output
(Bottom Gate)
All Other Pins
PGOOD
SYNC
Current Sense Amplifier
LX
LG
−5
−10
V < 200 ns
−0.3
−5
V < 200 ns
−0.3, −1
V < 1
ms
−0.3, −1
V < 1
ms
−0.3, −1
V < 1
ms
−0.3, −1
V < 1
ms
V
V
V
V
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
http://onsemi.com
3
NCP5230
THERMAL INFORMATION
Rating
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Operating Junction Temperature Range
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
QFN Package
Symbol
R
qJA
R
qJC
T
J
T
A
T
STG
MSL
Typ
60
18
0 to 125
0 to 85
−55
to +150
1
Unit
°C/W
°C/W
°C
°C
°C
−
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: 0°C < T
A
< 85°C; 4.5 V < VCC < 13.2 V; C
VCC
= 0.1
mF
Parameter
SUPPLY OPERATING CONDITIONS
VCC Voltage Range
VCCP Voltage Range
dV/dt on VCC (Note 1)
dV/dt on VCCP (Note 1)
VCC AND BOOT INPUT SUPPLY CURRENT
VCC Operating Current
VCC Supply Current
VCCP INPUT SUPPLY CURRENT
VCCP Operating Current
UG and LG Open
VCCP Supply Current
VCC SUPPLY VOLTAGE
VCC UVLO Start Threshold
VCC UVLO Hysteresis
VCCP SUPPLY VOLTAGE
VCCP UVLO Start Threshold
VCCP UVLO Hysteresis
ERROR AMPLIFIER COMP
Open Loop DC Gain (Note 1)
Open Loop Unity Gain Bandwidth (Note 1)
Slew Rate (Note 1)
VREF
Internal Reference Voltage
Output Voltage Accuracy
CURRENT SENSE AMPLIFIERS
Common Mode Input Voltage Range
(Note 1, GNG, output within 10mV)
Common Mode Input Voltage Range
(Note 1, GNG, output within 10 mV)
V
CC
≤
7.5 V
V
CC
> 7.5 V
−0.3
−0.3
3.5
5.5
V
V
V
out
to FBG excluding external resistor divider
tolerance
−0.5
0.800
0.5
V
%
COMP pin to GND with 100 pF load
15
120
18
8.0
dB
MHz
V/ms
200
4.2
V
mV
V
CC
Rising
V
CC
Rising or Falling
300
4.50
V
mV
V
CCP
= 5 V, EN = High
V
CCP
= 12 V, EN = High
V
CCP
= 5 V, EN = Low
V
CCP
= 12 V, EN = Low
3.5
5.0
200
mA
mA
V
CC
= 5 V, EN = High
V
CC
= 12 V, EN = High
V
CC
= 5 V, EN = Low
V
CC
= 12 V, EN = Low
5.0
400
mA
uA
4.5
4.5
−10
−10
13.2
13.2
10
10
V
V
V/ms
V/ms
Test Conditions
Min
Typ
Max
Unit
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
http://onsemi.com
4
NCP5230
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: 0°C < T
A
< 85°C; 4.5 V < VCC < 13.2 V; C
VCC
= 0.1
mF
Parameter
Test Conditions
Min
Typ
Max
Unit
OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)
Switching Frequency Accuracy
OSC Gain (Note 1)
Disable threshold
MODULATORS (PWM Comparators)
Minimum Pulse Width
Minimum Turn Off Time (LG on)
Magnitude of the PWM Ramp
Maximum Duty Cycle
Minimum Skip mode frequency
SOFT−START
Soft Start Time @ 200 kHz
SOFT−OFF
Soft OFF bleeding resistor
OVER CURRENT PROTECTION
First Over Current Threshold
Second Over Current Threshold
SYNC PIN
Synchronization Input
Synchronization Input
PROTECTION AND PGOOD
Output Voltage
OVP Threshold
UVP Threshold
Unlatched Overvoltage Threshold
Power Good High Delay (Note 1)
Power Good Low Delay (Note 1)
ZERO CURRENT DETECTION (LX Pin)
Blanking Time before Zero Current
Detection (Note 1)
Capture Time for LX Voltage (Note 1)
Negative LX detection voltage
Positive LX detection voltage
Time for V
th
adjustment and settling time
(Note 1)
Initial Negative Current Detection
Threshold Voltage Set Point (Note 1)
V
th
adjustable Range (Note 1)
Blanking Time after LG is < 1.0 V
Time to capture LX voltage once LG is < 1.0 V
(must be within dead time limits)
V
bdls
V
bdhs
300 kHz
LX−GND, Includes
±
2 mV Offset Range
−16
150
0.2
3.0
1.0
0
15
300
0.5
40
20
450
1.0
3.7
ns
ns
mV
V
ms
mV
mV
Logic Low, Sinking 4 mA
VSEN rising above 1.25 * V
ref
VSEN falling below 0.75 * V
ref
V
th_disoff
with respect to 0.5 V
ref
117
70
40
125
75
50
0.4
130
80
60
50
1
V
%
%
%
ms
ms
VIL, square wave
VIH, square wave
2.5
1.0
V
V
CSP−CSN, 4xMasking
CSP−CSN, Immediate action
17
20
30
23
mV
mV
R
dis
120
W
1024 clock cycles, OSC/EN open
5.12
ms
F
sw
= 200 kHz, OSC open
F
sw
= 200 kHz, OSC open
V
IN
= 5 V or 12 V
OSC/EN = OPEN
In light load, maximum time for LG to turn on
after HG turns off
80
30
250
90
350
1.50
95
450
ns
ns
V
%
kHz
R
OSC
/EN pin, V
dis_th
R
OSC
open
−10
10
0.75
10
%
kHz /
mA
V
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
