QSpan (CA91L860B) & QSpan II (CA91L862A) Differences Summary
1
1.
Introduction
This document identifies the software and hardware changes between the QSpan
II (CA91L862A) device and the QSpan (CA91L860B) device. This document is
intended to be used for reference purposes and assumes the reader is familiar
with the QSpan family of devices. It is the intent of this document to make the
transition from QSpan to QSpan II an easier process for our customers. For more
detail on the individual registers and their additional functionality, refer to the
QSpan and QSpan II User Manual. The three sections Hardware, Software, and
Backwards Compatibility will correspond to package differences (ie. new pins),
QSpan II configuration (ie. new registers), functional differences (ie. anything
relating to device operation).
Please ensure that you have the most recent version of this document, which is
available on the web at
www. tundra.com
or directly from Tundra or one of its
representatives.
Be sure to visit the Tundra
Designers’ Support Tools
at
www.tundra.com
for the
latest product updates and technical discussions.
2.
Hardware
The Hardware section will consist of package differences. For information on
what functionality these new pins add to the QSpan II, please refer to the QSpan
II User Manual. The new QSpan II pins are defined in Table 1 and the AC
signalling characteristics are shown in Table 3. The redefined pin of QSpan II
production part is defined in Table 2 and Chapter 4, note 4. Please note that for
all inputs and bidirectional signals, there have been internal resistors added to
allow these previous no-connect signals to be backwards compatible. If new
designs do not want to use any new functionality, these signals can be left as no-
connects.
8091862.AN002.06
QSpan (CA91L860B) & QSpan II (CA91L862A) Differences Summary
Hardware
2
Table 1: New Pin Descriptions in QSpan IIZ1
DP[3:0]
Bidirectional
Data Parity: provides the parity information for the data on D[31:0]. It is valid on the same clock as the data.
ENUM#
Open Drain Output
Hot Swap Event Interrupt: notifies the PCI host that either a board has been inserted or is about to be extracted.
EXT_GNT#[6:1]
Output
External Grant: used by the QSpan II to indicate to an external device that it has been granted access to the PCI bus
EXT_REQ#[6:1]
Bidirectional
External Request: used by an external device to indicate to the QSpan II PCI bus arbiter that it wants ownership of the PCI bus. The QSpan II drives the unused
EXT_REQ#[6:1] pins high when an external arbiter is used.
HS_HEALTHY
Input
Hot Swap Healthy: QSpan II internally OR’s this input with PCI reset (RST#) to determine when back-end power is stable.
HS_LED
Output
Hot Swap LED Control: This signal is driven by QSpan II to control the status of the LED. The signal is driven low to turn on the LED during the hardware
and software connection stages. The signal is tri-stated during normal operation to turn off the LED.
HS_SWITCH
Input
Hot Swap Switch: QSpan II uses this input to monitor the state of the Hot Swap board ejector latch. A low value on this signal indicates that the ejector latch is
open.
PCI_ARB_EN
Input
PCI Arbiter Enable: If PCI_ARB_EN is sampled high at the negation of Reset, the QSpan II’s PCI bus arbiter is enabled and will function as the PCI bus
arbiter.
PCI_DIS
Input
PCI Configuration Disable: This is a power-up option that makes the QSpan II hold off on ENUM# assertion and retry PCI configuration cycles to allow the
Host processor to perform local configuration. QSpan II accepts PCI configuration cycles after the PCI_DIS bit is cleared in the MISC_CTL2 register.
PME#
Open Drain Output
Power Management Event Interrupt: This signal is asserted to request a change in its current power management state and/or to indicate that a power
management event has occurred.
TEST1
Input
This is a manufacturing test input that should be left open. This pin has an internal pull-up resistor.
TEST2
Input
This is a manufacturing test input that should be left open. This pin has an internal pull-down resistor.
TEST3
Input
This is a manufacturing test input that should be left open. This pin has an internal pull-down resistor.
QSpan (CA91L860B) & QSpan II (CA91L862A) Differences Summary
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
