P R E L I M I N A RY I N F O R M AT I O N
MK2705
Audio Clock Source
Description
The MK2705 provides synchronous clock generation
for audio sampling clock rates derived from an MPEG
stream, or can be used as a standalone clock source
with a 27 MHz crystal. The device uses the latest PLL
technology to provide good phase noise and long term
jitter characteristics in a small 8 pin package.
Please contact ICS if you have a requirement for an
input and output frequency not included here - we can
rapidly modify this product to meet special
requirements.
Features
•
•
•
•
•
•
•
Packaged in 8 pin (150 mil wide) SOIC
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Independant output voltage
Support for 256 times sampling rate
Block Diagram
VDD
VDDO
S0
S1
X1
27 MHz
crystal or
clock input
Crystal
Oscillator
PLL Clock
Synthesis
and Control
Circuitry
CLK
X2
GND
MDS 2705 A
1
Revision 090502
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
Preliminary Information
MK2705
Audio Clock Source
Pin Assignment
X1/REFIN
VDD
S0
GND
1
2
3
4
8
7
6
5
X2
VDDO
S1
CLK
Output Clock Selection Table
S1
0
0
1
1
S0
0
1
0
1
Input
Frequency
(MHz)
27
27
27
27
Output
Frequency
(MHz)
8.192
11.2896
12.288
24.576
8 pin SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/REFIN
VDD
S0
GND
CLK
S1
VDDO
X2
Pin
Type
Input
Power
Input
Power
Output
Input
Power
Input
Pin Description
Connect this pin to a crystal or clock input
Power supply for crystal oscillator and PLL.
Output frequency selection. Determines output frequency per table above. On chip pull up.
Connect to ground.
Clock output.
Output frequency selection. Determines output frequency per table above. On chip pull up.
Power supply for output stage.
Connect this pin to a crystal. Leave open if using a clock input.
MDS 2705 A
2
Revision 090502
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
Preliminary Information
MK2705
Audio Clock Source
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(C
L
- 6) where C is the
load capacitor connected to X1 and X2, and C
L
is the
specified value of the load capacitance for the crystal.
A typical crystal C
L
is 18pF, so C = 2(18 - 6) = 24pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2705 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK2705 should use one common connection to the
PCB power plane as shown in the diagram on the next
page. The ferrite bead and bulk capacitor help reduce
lower frequency noise in the supply that can lead to
output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33Ω series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2705. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Recommended Power Supply Connection for
Optimal Device Performance
VDD Pin
Connection to 3.3V
Power Plane
Ferrite
Bead
VDD Pin
Bulk Decoupling Capacitor
(such as 1
µF
Tantalum)
0.01
µF
Decoupling Capacitors
Both VDD pins must be connected to the same voltage.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
MDS 2705 A
3
Revision 090502
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
Preliminary Information
MK2705
Audio Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2705. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
4.5V
Rating
-0.5V to VDD+0.5V
0 to +70°C
-65 to +150°C
175°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
°C
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Supply Current
Standby Supply Current
Short Circuit Current
Nominal Output Impedance
Input Capacitance
Actual mean frequency error
versus target
Internal pull-up resistor value
Symbol
VDD
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
IDDPD
I
OS
Z
OUT
Conditions
Min.
3.0
2
Typ.
Max.
3.6
0.8
Units
V
V
V
V
V
I
OH
= -4 mA
I
OH
= -25 mA
I
OL
= 25mA
No Load
VDD-0.4
2.4
0.4
TBD
V
mA
µA
mA
Ω
pF
ppm
Each output
input pins
Note 2
±100
20
7
0
TBD
MDS 2705 A
4
Revision 090502
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
Preliminary Information
MK2705
Audio Clock Source
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Crystal Frequency
Output Duty Cycle
Output Clock Rise Time
Output Clock Fall Time
Jitter, short term
Jitter, long term
Single sideband phase noise
Symbol
t
OD
t
OR
t
OF
Conditions
Measured at VDD/2
20% to 80%
80% to 20%
Min.
45
Typ.
27
49 to 51
Max.
55
1.5
1.5
Units
MHz
%
ns
ns
ps p-p
ps p-p
dBc
250
10 us delay
10 kHz offset
500
-110
MDS 2705 A
5
Revision 090502
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
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