TH7426A/27A
NEAR INFRARED InGaAs LINEAR IMAGE SENSOR
300 PIXELS
DESCRIPTION
These devices are based on a 300 InGaAs photodiode li-
near array, with a 26µm pitch, using an in line pixel layout or
a staggered pixel layout.
Two 150:1 CCD multiplexor chips, offering memory and de-
layed readout capability, are hybridized on both sides of the
photodiode array so as to build a complete module.
Specially designed to allow an accurate butting, those mo-
dules could be tied together on request so as to provide an
array extension with only one dead pixel at the splice.
These devices are also available in a full CMOS interface
version :
TH74KA26A/TH74KA27A or TH74KB26A/TH74KB27A.
MAIN FEATURES
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APPLICATIONS
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Near infrared spectral response: 0.8µm to 1.7µm
Room temperature operation
Low noise
High detectivity, wide dynamic range (>10 000)
High linearity, high Modulation Transfer Function (MTF)
High output data rate : up to 6 MHz
Intrinsic antiblooming
Built in thermoelectric cooler and temperature sensor
available
Accurate mechanical indexes (ready to mount)
Suited for Near Infrared imaging
Thermal imaging in the 200°C to 800°C range
High resolution multichannel spectrometry
Fluorescence free Raman spectrophotometry
On-line inspection and monitoring
SELECTION GUIDE
REFERENCE
TH7426A
TH7427A
TH7428A
TH7429A
PIXEL COUNT
299
299
599
599
LAYOUT
In line
Staggered
In line
Staggered
PIXEL AREA
20x30µm²
30x30µm²
20x30µm²
30x30µm²
PITCH
26µm
26µm
26µm
26µm
NUMBER OF
VIDEO OUTPUTS
2
2
4
4
March 1998
1/20
TH7426A/27A
GEOMETRICAL CHARACTERISTICS
ELEMENT BLOCK DIAGRAM
2/20
TH7426A/27A
ABSOLUTE MAXIMUM RATINGS
Supply voltages (compare to Vss, at any pin)
Transient voltages (compare to Vss, at any pin)
DC current (at any pin),
Except
- thermoelectric cooler pins
except
- temperature sensor
Operating temperature (temperature variation limited to 6°C/min)
Storage temperature (temperature variation limited to 6°C/min)
Electrostatic discharge sensitivity, MIL-STD-883 method 3015
0 to +20V
0 to +25V
10mA
6A
+/-3mA
-40 to +85°C
-40 to +85°C
device Class 1
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent devices failure. Functionality at
or above these limits is not implied. Exposure to maximum ratings for extended periods may affect device reliability.
To avoid any performance degradation,the device must be handled with grounded bracelet and stored in the conductive
packing used for shipment.
TABLE 1 - ELECTRO-OPTICAL CHARACTERISTICS
15°C internal operating temperature, 3ms integration time, typical voltage input (otherwise specified).
Parameter
Dark voltage signal
mean
isolated pixels
(photodiode dark current)
Noise in darkness
mean
isolated pixels
(rms)
Symbol
Min.
V
D
( I
D
)
σV
D
R
PRNU
λc
dλc/dT
MTF
0.35
0.55
Vsat
2.5
0.50
0.68
0.54
0.73
0.35
0.35
2.5
0.50
0.50
0.54
0.54
V
TH 7426
Typ.
3
100
0.6
200
1
10
+/-10
1
1.66
1.68
1.1
1.73
1.66
1
1.68
1.1
173
15
+/-10
0.8
200
1.2
Max.
Min
TH 7427
Typ.
4
120
Max.
mV
mV
pA
µV
mV
Vcm²/µJ
%
%
µm
nm/°C
See Fig. 3-4-5
See Fig. 6
See note (1)
Unit
Remarks
Absolute photo response
mean
non uniformity
non linearity over 1.5V range
Spectral response
Cut-off wavelength
Temperature shift
Modulation transfer function
across array
along array
Output saturation voltage
At 50% R(λ)
max
At 19.2 lp/mm
See note (2)
Depends on
preload level.
See Fig. 7
BW=1Hz
BW=167Hz
BW=167Hz
Noise equivalent power at
λ=1.65µm
Specific detectivity at
λ=1.65µm
Electron to voltage conversion factor
Quantum efficiency
Image grade
(number of blemishes)
NEP
0.35
40
6.7
5.10
12
8.10
11
0.26
0.8
1
5
10
NA
0.35
40
4.4
6.10
12
1.10
12
0.26
0.8
1
5
10
NA
fW
fW
nWcm
-2
D*
Fc
QE
J
K
O
E
cmHz
1/2
W
-1
BW=1Hz
cmHz
1/2
W
-1
BW=167Hz
µV/e
e/ph
See Fig. 5
See note (3)
Electrical sample
Note : 1
Already taken into account in mean V
D
(V
D
= Id TI Fc ; TI=Integration time ; q = 1.6 10
-19
C)
q
Note : 2
“Maximum value” is the theoretical value computed using the corresponding diode size
Note : 3
a pixel is considered as a blemish if :
or
- its dark voltage is higher than isolated pixel max value
or
- its noise is higher than isolated pixel noise max value
or
- its PRNU is higher than +/- 10 %
3/20
TH7426A/27A
TABLE 2 - CONNECTION DIAGRAMS
Pin n° EVEN Sym-
Mo-
bol
dule #
1...2
3...6
7...9
10
11...14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31...34
35...42
43
Notes
Notes
Notes
Notes
:
:
:
:
1
2
3
4
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
NC
TS
NC
DNC
NC
VDD
VOS
GND
VSS
φR
VDR
VGS
VN
φL1
RE
φL2
Designation
Pin n° ODD Sym-
Mo- bol
dule #
44...51
52...55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72...75
76
77...79
80...83
84
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TC+
NC
VG1
φX
φPL
Designation
Not connected
Temperature sensor see note (3)
Not connected
Do not connect see note (4)
Not connected
Output amplifier drain & RE supplies
Video output signal (pixels 0-298)
Video ground
CCD substrate bias (phases return)
CCD reset clock
Reset bias
Output gate bias
Photodiode substrate bias see note (1)
Shift register clock 1
Read enable control signal
(pixels 0-298)
Shift register clock 2 (gated by RE)
Thermoelectric cooler (positive node)
see notes (2) (3)
Not connected
Lateral skimming gate bias
Photodiode lateral transfer clock
Electrical injection clock
VGL1 Preload skimming gate bias
VGL2 Preload storage gate bias
φL2
RE
φL1
VN
VGS
VDR
φR
VSS
GND
VOS
VDD
NC
DNC
NC
TS
NC
Shift register clock 2 (gated by RE)
Read enable control signal
(pixels 1-299)
Shift register clock 1
Photodiode substrate bias see note (1)
Output gate bias
Reset bias
CCD reset clock
CCD substrate bias (phases return)
Video ground
Video output signal (pixels 1-299)
Output amplifier drain & RE supplies
Not connected
Do not connect see note (4)
Not connected
Temperature sensor see note (3)
Not connected
VGL2 Preload storage gate bias
VGL1 Preload skimming gate bias
φPL
φX
VG1
NC
TC-
NC
Electrical injection clock
Photodiode lateral transfer clock
Lateral skimming gate bias
Not connected
Thermoelectric cooler (negative
node) see notes (2) (3)
Not connected
Pin 22 and 64 are internally connected together
In each group every pins must be connected and tied together in order to lower pin current density
Not connected on non cooled package
DNC (Do Not Connect). Pins which are internally connected and must not be used.
4/20
TH7426A/27A
PIN DESCRIPTION
Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.
F
PL
This is the preload injection stage electrical input. Each
Φ
PL
pulse down overfills preload storage capacitance with
electrons.
Φ
PL
is connected to a diode cathode which anode is internally tied to Vss.
VGL1
This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance
will be biased. Thus it drives preload level.
VGL2
This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while V
GL1
deter-
mines its top level. Preload capacitance thus is charged up proportionately to (V
GL2
- V
GL1
) bias difference.
F
L1
F
L2
This is the main register storage grid clock. Charges are stored under
Φ
L1
when transfer is disabled (RE at low le-
vel).
F
L1
is also used for lateral transfers to input nodes.
This is the main register transfer grid clock.
Φ
L2
is used to isolate
F
L1
content during lateral transfers. The main re-
gister is beginning and ending with
F
L2
which therefore controls main register access and outputs.
F
L2
is gated by
RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating
each
F
L1
well.
This is the “Read Enable” input. When high, it allows
Φ
L2
input connection to main register, when low, main register
corresponding grids are pulled down whatever
F
L2
input level is.
This input helps to serially read out two or more multiplexors with one single
F
L2
signal for all. Data are stored into
the main register as long as RE is low, thus read out can occur later on.
This is the lateral transfer grid command. Lateral transfer is allowed when
F
X
is at high level.
F
X
is common to all
input nodes, all photodiode information is collected at the same time.
This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same
from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading
to overcrossing V
G1
level are skimmed back into
Φ
L1
main register wells.
This is the InGaAs photodiode common cathode bias. V
N
is available on odd and ev en side, however, both pins are
connected together, to photodiode substrate.
This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges
to be read out when
Φ
L2
is at low level.
This is the read out capacitance reset bias. After each single read out, read out capacitance is cleared off (reset) to
V
DR
level, during
F
R
clock high state.
RE
F
X
VG1
VN
VGS
VDR
5/20
FPGA/CPLD
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