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HY57V641620HGLT-55

产品描述Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
产品类别存储    存储   
文件大小83KB,共12页
制造商SK Hynix(海力士)
官网地址http://www.hynix.com/eng/
下载文档 详细参数 选型对比 全文预览

HY57V641620HGLT-55概述

Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V641620HGLT-55规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称SK Hynix(海力士)
零件包装代码TSOP2
包装说明TSOP2, TSOP54,.46,32
针数54
Reach Compliance Codecompliant
ECCN代码EAR99
访问模式FOUR BANK PAGE BURST
最长访问时间5 ns
其他特性AUTO/SELF REFRESH
最大时钟频率 (fCLK)182 MHz
I/O 类型COMMON
交错的突发长度1,2,4,8
JESD-30 代码R-PDSO-G54
长度22.23 mm
内存密度67108864 bit
内存集成电路类型SYNCHRONOUS DRAM
内存宽度16
功能数量1
端口数量1
端子数量54
字数4194304 words
字数代码4000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织4MX16
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSOP2
封装等效代码TSOP54,.46,32
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度)NOT SPECIFIED
电源3.3 V
认证状态Not Qualified
刷新周期4096
座面最大高度1.194 mm
自我刷新YES
连续突发长度1,2,4,8,FP
最大待机电流0.002 A
最大压摆率0.16 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式GULL WING
端子节距0.8 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度10.16 mm

文档预览

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HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
D E S C R IP T IO N
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3±
0 . 3 V
power supply
Note)
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Data mask function by UDQM or LDQM
Internal four banks operation
O R D E R IN G IN F O R M A T IO N
Part No.
HY57V641620HGT-5/55/6/7
HY57V641620HGT-K
HY57V641620HGT-H
HY57V641620HGT-8
HY57V641620HGT-P
HY57V641620HGT-S
HY57V641620HGLT-5/55/6/7
HY57V641620HGLT-K
HY57V641620HGLT-H
HY57V641620HGLT-8
HY57V641620HGLT-P
HY57V641620HGLT-S
C lock Frequency
200/183/166/143MHz
133MHz
133MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
100MHz
200/183/166/143MHz
133MHz
133MHz
Low power
125MHz
100MHz
100MHz
4Banks x 1Mbits
x16
LVTTL
400mil 54pin TSOP II
N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01

HY57V641620HGLT-55相似产品对比

HY57V641620HGLT-55 HY57V641620HGLT-6 HY57V641620HGLT-8 HY57V641620HGLT-H HY57V641620HGLT-K HY57V641620HGLT-S HY57V641620HGLT-5 HY57V641620HGLT-7
描述 Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 4.5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
厂商名称 SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士)
零件包装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
包装说明 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32
针数 54 54 54 54 54 54 54 54
Reach Compliance Code compliant compliant compliant unknown unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 5 ns 5.4 ns 6 ns 5.4 ns 5.4 ns 6 ns 4.5 ns 5.4 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 182 MHz 166 MHz 125 MHz 133 MHz 133 MHz 100 MHz 200 MHz 143 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
交错的突发长度 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
JESD-30 代码 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54
长度 22.23 mm 22.23 mm 22.23 mm 22.23 mm 22.23 mm 22.23 mm 22.23 mm 22.23 mm
内存密度 67108864 bit 67108864 bit 67108864 bit 67108864 bit 67108864 bit 67108864 bit 67108864 bit 67108864 bit
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 16 16 16 16 16 16 16 16
功能数量 1 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1 1
端子数量 54 54 54 54 54 54 54 54
字数 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words
字数代码 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 4MX16 4MX16 4MX16 4MX16 4MX16 4MX16 4MX16 4MX16
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
封装等效代码 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 4096 4096 4096 4096 4096 4096
座面最大高度 1.194 mm 1.194 mm 1.194 mm 1.194 mm 1.194 mm 1.194 mm 1.194 mm 1.194 mm
自我刷新 YES YES YES YES YES YES YES YES
连续突发长度 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP
最大待机电流 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A
最大压摆率 0.16 mA 0.16 mA 0.16 mA 0.16 mA 0.16 mA 0.16 mA 0.17 mA 0.16 mA
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3 V 3 V 3 V 3 V 3.135 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
宽度 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
JESD-609代码 - - - e6 e6 e6 e6 e6
端子面层 - - - TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH
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