Freescale Semiconductor
Data Sheet, Technical Data
Document Number: MCIMX27EC
Rev. 1.7, 05/2011
i.MX27 and i.MX27L
i.MX27 and i.MX27L
Data Sheet
Multimedia Applications
Processor
1
Introduction
1.
Package Information
Plastic Package
Case 1816-01
(MAPBGA–404)
Case 1931-04
(MAPBGA-473)
Ordering Information
See
Table 1 on page 4
for ordering information.
The i.MX27 and i.MX27L (MCIMX27/MX27L)
Multimedia Applications Processors represents the next
step in low-power, high-performance application
processors. Unless otherwise specified, the material in
this data sheet is applicable to both the i.MX27 and
i.MX27L processors and referred to singularly
throughout this document as i.MX27.
The i.MX27L does not include the following features:
ATA-6 HDD Interface, Memory Stick Pro, VPU:
MPEG-4/ H.263/H.264 HW encoder/decoder, and
eMMA (PrP processing, CSC, deblock, dering).
Based on an ARM926EJ-S™ microprocessor core, the
i.MX27/27L processor provides the performance with
low-power consumption required by modern digital
devices such as the following:
• Feature-rich cellular phones
• Portable media players and mobile gaming
machines
• Personal digital assistants (PDAs) and wireless
PDAs
2.
3.
4.
5.
6.
7.
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description and Application Information . . . . 4
2.1. ARM926 Microprocessor Core Platform . . . . . . . . 4
2.2. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1. Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . 35
3.2. EMI Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . 35
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 40
4.1. i.MX27/iMX27L Chip-Level Conditions . . . . . . . . 40
4.2. Module-Level Electrical Specifications . . . . . . . . 43
4.3. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 54
Package Information and Pinout . . . . . . . . . . . . . . . . 109
5.1. Full Package Outline Drawing (17 mm
× 17
mm) 109
5.2. Pin Assignments (17 mm
×
17 mm) . . . . . . . . . 110
5.3. Full Package Outline Drawing (19 mm
× 19
mm) 129
5.4. Pin Assignments (19 mm
×
19 mm) . . . . . . . . . 130
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . 150
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Introduction
•
•
Portable DVD players
Digital cameras
The i.MX27/MX27L processor features the advanced and power-efficient ARM926EJ-S core operating at
speeds up to 400 MHz, and is optimized for minimal power consumption using the most advanced
techniques for power saving (for example, DPTC, power gating, and clock gating). With 90 nm technology
and dual Vt, the i.MX27/MX27L device provides the optimal performance vs. leakage current balance.
The performance of the i.MX27/MX27L processors are both boosted by an on-chip cache system, and
features peripheral devices, such as an MPEG-4, H.263, an H.264 video codec (up to D1—720 x 486—@
30 FPS), LCD, eMMA_lt, and CMOS Sensor Interface controllers.
The i.MX27/MX27L processors supports connections to various types of external memories, such as
266-MHz DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX27/MX27L devices can be
connected to a variety of external devices using technology, such as high-speed USBOTG 2.0, the
Advanced Technology Attachment (ATA), Multimedia/Secure Data (MMC/SDIO), and CompactFlash.
NOTE
The i.MX27L does not support the ATA-6 HDD interface.
1.1
Features
The MX27/MX27L processors are targeted for video and voice over-IP (V2IP) and smart remote
controllers. It also provides low-power solutions for any high-performance and demanding multimedia and
graphics applications.
The systems include the following features:
• Multi-standard video codec (i.MX27 only)
— MPEG-4 part-II simple profile encoding/decoding
— H.264/AVC baseline profile encoding/decoding
— H.263 P3 encoding/decoding
— Multi-party call: one stream encoding and two streams decoding simultaneously
— Multi-format: encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously
— On-the-fly video processing that reduces system memory load (for example, the
power-efficient viewfinder application with no involvement of either the memory system or the
ARM CPU)
• Advanced power management (i.MX27/27L)
— Dynamic process and temperature compensation
— Multiple clock and power domains
— Independent gating of power domains
• Multiple communication and expansion ports
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
2
Freescale Semiconductor
Introduction
1.2
Block Diagram
Figure 1
shows the i.MX27 simplified interface block diagram.
DDR/
SDRAM
NOR/NAND
Flash
LCD Display
Camera
M3IF
SDRAMC
NFC
WEIM
PCMCIA/CF
LCDC
SLCDC
CSI
ARM926
Platform
AP Peripherals
AUDMUX
SSI (2)
CSPI (3)
I
2
C (2)
UART (6)
USBOTG HS
1-Wire
FEC
ATA
SDHC (3)
MSHC
GPIO
JTAG
CRM
PWM
KPP
ARM926EJ-S
L1 I/D cache
AHB Switch Fabric
VRAM
AITC
ETM9
eMMA-lt
iROM
10/100
ETH XVR
Security
SAHARA2
RTIC
SCC
IIM
Video Codec
DMA
Note: The i.MX27L does not support the following:
• ATA-6 HDD Interface
• Memory Stick Pro
• VPU: MPEG-4/.263/H.264 HW encoder/decoder
• eMMA (PrP processing, CSC, deblock, dering)
Freescale Semiconductor
Audio/Power
Management
JTAG
IrDA
XVR
Timers
WDOG
GPT (6)
RTC
Application Processor Domain (AP)
Bluetooth
WLAN
USBOTG
XVR
MMC/SDIO
Keypad
Access
Conn.
Figure 1. i.MX27/MX27L Simplified Interface Block Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
3
Functional Description and Application Information
1.3
Ordering Information
Table 1. Ordering Information
Device
MCIMX27VOP4A
MCIMX27LVOP4A
MCIMX27MOP4A
MCIMX27LMOP4A
MCIMX27VJP4A
MCIMX27LVJP4A
MCIMX27MJP4A
MCIMX27LMJP4A
Temperature
–20° C to +85° C
–20° C to +85° C
–40° C to +85° C
–40° C to +85° C
–20° C to +85° C
–20° C to +85° C
–40° C to +85° C
–40° C to +85° C
Package
1816-01
1816-01
1931-04
1931-04
1816-01
1816-01
1931-04
1931-04
Table 1
provides ordering information for the MAPBGA, lead-free packages.
2
2.1
Functional Description and Application Information
ARM926 Microprocessor Core Platform
The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6
×
3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex.
• The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master
Port 0.
• The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.
Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the
MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB
is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL
memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred
to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the
user to trade off between high performance and high-code density. The ARM926EJ-S processor includes
features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time
(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and
provides a complete high-performance processor subsystem, including the following:
• An ARM9EJ-S integer core
• A Memory Management Unit (MMU)
• Separate instruction and data AMBA AHB bus interfaces
• ETM and JTAG-based debug support
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
4
Freescale Semiconductor
Functional Description and Application Information
The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other
application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM
architecture version 5TEJ.
The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports
of the MAX, are designed to support connections to multiple AHB masters external to the platform. An
external arbitration AHB control module is needed if multiple external masters are desired to share an
ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform
support seamless connection to a single master with no external interface logic required.
A primary AHB MUX (PAHBMUX) module performs address decoding, read data muxing, bus
watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control
module (CLKCTL) is provided to support a power-conscious design methodology, as well as
implementation of several clock synchronization circuits.
2.1.1
Memory System
The ARM926EJ-S complex includes 16-Kbyte Instruction and 16-Kbyte Data caches. The embedded
45-Kbyte SRAM (VRAM) can be used to avoid external memory accesses or it can be used for
applications. There is also a 24-Kbyte ROM for bootstrap code.
2.2
Module Inventory
Table 2
shows an alphabetical listing of the modules in the i.MX27/MX27L multimedia applications
processors. A cross-reference to each module’s section and page number goes directly to a more detailed
module description for additional information.
Table 2. Digital and Analog Modules
Block Mnemonic
1-Wire
®
Block Name
1-Wire Interface
Functional
Grouping
Connectivity
Peripheral
Brief Description
The 1-Wire module provides bi-directional communication
between the ARM926EJ-S and the Add-Only-Memory EPROM
(DS2502). The 1-Kbit EPROM is used to hold information
about battery and communicates with the ARM926 Platform
using the IP interface.
The AIPI acts as an interface between the ARM Advanced
High-performance Bus Lite. (AHB-Lite) and lower bandwidth
peripherals that conforms to the IP Bus specification, Rev 2.0.
AITC is connected to the primary AHB as a slave device. It
generates the normal and fast interrupts to the ARM926EJ-S
processor.
The ARM926EJ-S (ARM926) is a member of the ARM9 family
of general-purpose microprocessors targeted at multi-tasking
applications.
The ATA block is an AT attachment host interface. It interfaces
with IDE hard disc drives and ATAPI optical disc drives.
Section/
Page
2.3.1/9
AIPI
AHB-Lite IP
Interface
Module
ARM9EJ-S
Interrupt
Controller
ARM926EJ-S
Bus Control
2.3.2/10
AITC
Bus Control
2.3.3/10
ARM926EJS
CPU
2.3.4/10
ATA
Advanced
Technology(AT)
Attachment
Connectivity
Peripheral
2.3.5/11
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
5
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