74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
Rev. 04 — 19 May 2006
Product data sheet
1. General description
The 74LVT16501A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the
outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA to
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 883, method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
Philips Semiconductors
74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
i
C
io
I
CC
propagation delay An to Bn or
Bn to An
propagation delay An to Bn or
Bn to An
input capacitance (control pins)
input/output capacitance
(I/O pins)
quiescent supply current
Conditions
C
L
= 50 pF;
V
CC
= 3.3 V
C
L
= 50 pF;
V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
outputs disabled;
V
I/O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V
Min
-
-
-
-
-
Typ
1.9
1.9
3
9
70
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
µA
4. Ordering information
Table 2.
Ordering information
Package
Temperature range Name
74LVT16501ADL
−40 °C
to +85
°C
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT371-1
SOT364-1
Type number
74LVT16501ADGG
−40 °C
to +85
°C
74LVT16501A_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 19 May 2006
2 of 19
Philips Semiconductors
74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
Pin description
…continued
Pin
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Description
data input or output A4
data input or output A5
ground (0 V)
data input or output A6
data input or output A7
data input or output A8
data input or output A9
data input or output A10
data input or output A11
ground (0 V)
data input or output A12
data input or output A13
data input or output A14
voltage supply
data input or output A15
data input or output A16
ground (0 V)
data input or output A17
B-to-A output enable input (active LOW)
B-to-A latch enable input
ground (0 V)
B-to-A clock input (active rising edge)
data input or output B17
ground (0 V)
data input or output B16
data input or output B15
voltage supply
data input or output B14
data input or output B13
data input or output B12
ground (0 V)
data input or output B11
data input or output B10
data input or output B9
data input or output B8
data input or output B7
data input or output B6
ground (0 V)
data input or output B5
data input or output B4
data input or output B3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table 3.
Symbol
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
V
CC
A15
A16
GND
A17
OEBA
LEBA
GND
CPBA
B17
GND
B16
B15
V
CC
B14
B13
B12
GND
B11
B10
B9
B8
B7
B6
GND
B5
B4
B3
74LVT16501A_4
Product data sheet
Rev. 04 — 19 May 2006
5 of 19
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
