SM5842AP/APT
NIPPON PRECISION CIRCUITS INC.
High-Class Audio Multi-function Digital Filter
OVERVIEW
The SM5842AP/APT is a multi-function digital filter
IC, fabricated using NPC’s Molybdenum-gate
CMOS process, for digital audio reproduction equip-
ment. It features 8-times oversampling (interpola-
tion), independent left and right-channel digital
deemphasis, and soft muting functions. It accepts 16,
18, 20 or 24-bit input data, and outputs data in 18,
20, 22 or 24-bit format. It operates using either a
384fs or 256fs system clock at sampling frequencies
up to 48 kHz + 10% (384fs SM5842AP, 384/256fs
SM5842APT).
s
s
s
s
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• 256fs
- 13 MHz maximum frequency (at maximum
fs = 50.7 kHz, SM5842AP)
- 14.2 MHz maximum frequency (at maximum
fs = 55.2 kHz, SM5842APT)
Crystal oscillator circuit built-in
TTL-compatible input/outputs
5.0 ± 0.25 V supply
Molybdenum-gate CMOS process
28-pin plastic DIP
Filter Configuration
s
FEATURES
Functions
s
s
s
s
s
s
s
s
s
s
s
L/R 2-channel processing
8-times oversampling (interpolation)
•
≤
±0.00002 dB passband ripple
•
≥
117 dB stopband attenuation
Digital deemphasis
• 32/44.1/48 kHz sampling frequency (fs)
• 2-channel independent ON/OFF control
Soft muting
• 2-channel independent ON/OFF control
Input data format
• 2s complement, MSB first
- LR alternating, 16/18/20/24-bit serial, trail-
ing data
- LR alternating, 24-bit serial, leading data
- LR simultaneous, 24-bit serial, leading data
Output data format
• 2s complement, MSB first, LR simultaneous
• 18/20/22/24-bit serial
• BCKO burst (NPC format)
Dither round-up processing
• ON (dither rounding)/OFF (normal rounding)
control
25-bit internal data length
Jitter-free function for correct operation in the
presence of jitter between the system clock and
LRCI clock
• ON (jitter-free mode)/OFF (sync mode) control
256fs/384fs system clock selectable
• 384fs
- 21.2 MHz maximum frequency (at maximum
fs = 55.2 kHz)
s
s
Linear phase 3-stage FIR interpolation filter
• 169-tap 1st stage (fs to 2fs)
• 29-tap 2nd stage (2fs to 4fs)
• 17-tap 3rd stage (4fs to 8fs)
Deemphasis filter
- IIR filter configuration for accurate gain and
phase characteristics
26
×
24-bit parallel multiplier/32-bit accumulator
for high precision
Overflow limiter built-in
APPLICATIONS
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s
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CD players
DAT players
PCM systems
PINOUT
DI / INF2N
BCKI
CKSLN
INF1N
IW1N / DIL
XTI
XTO
VSS
CKO
IW2N / DIR
OW1N
OW2N
SYNCN
RSTN
1
28
LRCI
DG
BCKO
WCKO
DOL
DOR
VDD
DITHN
MUTEL
MUTER
FSEL2
FSEL1
DEMPL
SM5842AP/APT
14
15
DEMPR
NIPPON PRECISION CIRCUITS—1
SM5842AP/APT
PACKAGE DIMENSIONS
Unit: mm
28-pin plastic DIP
0° to 15°
13.8 0.2
+ 0.3
1.5
−0.05
3.8 0.1
BLOCK DIAGRAM
CKSLN LRCI
DI
/ INF2N BCKI
IW1N
/ DIL
IW2N
/ DIR
XTI
XTO
CKO
System
Clock
3.2 0.2
7.7 0.5
2.54
0.45 0.1
4.5 0.3
+
0.25
−
0.10
0.05
37.3 0.3
15.2
Input Data Interface
INF1N
RSTN
SYNCN
Timing
Controller
Filter and Attenuation Arithmetic block
DITHN
DEMPL
DEMPR
FSEL1
FSEL2
Deemphasis
Control
Output Data Interface
OW2N
MUTEL
MUTER
Mute Control
OW1N
V
SS
V
DD
BCKO WCKO DOL DOR
DG
NIPPON PRECISION CIRCUITS—2
SM5842AP/APT
PIN DESCRIPTION
Number
1
2
3
Name
DI/INF2N
BCKI
CKSLN
I/O
1
Ip
Ip
Ip
Description
Data input when INF1N is LOW, and input format select pin 2 when INF1N is HIGH.
Input bit clock
Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.
Input format select pin 1. INF1N and INF2N select the pin functions below.
Pin function selection
INF1N
LOW
LOW
HIGH
HIGH
DI/INF2N
LOW
LR alternating, trailing data
HIGH
LOW
HIGH
LR alternating, leading data
INF2N
LR simultaneous, leading data
DIL
DIR
DI
IW1N
IW2N
Input format
DI/INF2N
4
INF1N
Ip
IW1N/DIL
IW2N/DIR
Input bit length select pin 1 when INF1N is LOW, and left-channel data input when INF1N is HIGH.
IW1N and IW2N select the input data length.
INF1N
IW2N/DIL
LOW
5
IW1N/DIL
Ip
LOW
HIGH
HIGH
HIGH
6
7
8
9
10
XTI
XTO
VSS
CKO
IW2N/DIR
I
O
–
O
Ip
Oscillator input connection
Oscillator output connection
Ground
Oscillator output clock. Same frequency as XTI.
Input bit length select pin 2 when INF2N is LOW, and right-channel data input when INF2N is HIGH.
IW1N and IW2N select the input data length as shown in the table for pin 5.
Output length select bits.
11
OW1N
Ip
OW2N
LOW
LOW
12
OW2N
Ip
HIGH
HIGH
13
14
15
16
SYNCN
RSTN
DEMPR
DEMPR
Ip
Ip
Ip
Ip
OW1N
LOW
HIGH
LOW
HIGH
Output bit length
24 bits
22 bits
20 bits
18 bits
×
LOW
HIGH
×
18 bits
16 bits
24 bits
LOW
IW1N/DIR
LOW
HIGH
Input bit length
24 bits
20 bits
Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.
System reset. Reset operation when LOW, and normal operation when HIGH.
Right-channel deemphasis control signal. OFF when LOW, and ON when HIGH.
Left-channel deemphasis control signal. OFF when LOW, and ON when HIGH.
Deemphasis filter select inputs
17
FSEL1
Ip
FSEL1
LOW
LOW
FSEL2
LOW
HIGH
LOW
HIGH
Sampling frequency (fs)
44.1 kHz
48 kHz
Invalid setting
32 kHz
18
FSEL2
Ip
HIGH
HIGH
NIPPON PRECISION CIRCUITS—3
SM5842AP/APT
Number
19
20
21
22
23
24
25
26
27
28
Name
MUTER
MUTEL
DITHN
VDD
DOR
DOL
WCKO
BCKO
DG
LRCI
I/O
1
Ip
Ip
Ip
–
O
O
O
O
O
Ip
Description
Right-channel mute signal. Muting when HIGH, and normal output when LOW.
Left-channel mute signal. Muting when HIGH, and normal output when LOW.
Dither processing control. ON when LOW, and OFF when HIGH.
5 V supply
Right-channel data output
Left-channel data output
Output word clock
Output bit clock
Deglitched output
Input data sample rate (fs) clock
1. I = input, Ip = Input with pull-up resistor, O = output
NIPPON PRECISION CIRCUITS—4
SM5842AP/APT
SPECIFICATIONS
Absolute Maximum Ratings
V
SS
= 0 V
Parameter
Supply voltage range
Input voltage range
Storage temperature range
Power dissipation
Soldering temperature
Soldering time
Symbol
V
DD
V
IN
T
stg
P
D
T
sld
t
sld
Rating
−0.3
to 7.0
−0.3
to V
DD
+
0.3
−40
to 125
550
255
10
Unit
V
V
°C
mW
°C
s
Recommended Operating Conditions
V
SS
= 0 V
Parameter
Supply voltage range
Operating temperature range
Symbol
V
DD
SM5842AP
T
opr
SM5842APT
Condition
Rating
4.75 to 5.25
−20
to 80
−20
to 70
Unit
V
°C
DC Electrical Characteristics
V
DD
= 4.75 to 5.25 V, V
SS
= 0 V, T
a
=
−20
to 80
°C
Rating
Parameter
Current consumption
XTI HIGH-level input voltage
XTI LOW-level input voltage
HIGH-level input voltage
2
LOW-level input voltage
2
HIGH-level output voltage
3
LOW-level output voltage
3
XTO HIGH-level output voltage
XTO LOW-level output voltage
XTI HIGH-level input current
XTI LOW-level input current
LOW-level input current
2
Input leakage current
2
Symbol
I
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
I
LH
I
LL1
I
LL2
I
IH
I
OH
=
−0.4
mA
I
OL
= 1.6 mA
I
OH
=
−1.0
mA
I
OL
= 1.0 mA
V
IN
= V
DD
V
IN
= 0 V
V
IN
= 0 V
V
IN
= V
DD
Condition
min
V
DD
= 5.0 V
1
–
0.7V
DD
–
2.4
–
2.5
–
V
DD
−
0.5
–
–
–
–
–
typ
60
–
–
–
–
–
–
–
–
10
10
10
–
max
80
–
0.3V
DD
–
0.5
–
0.4
–
0.4
20
20
20
1.0
mA
V
V
V
V
V
V
V
V
µA
µA
µA
µA
Unit
1. f
SYS
= 256fs = 14.2 MHz (CKSLN = LOW), no output load
2. Pins DI/INF2N, BCKI, CKSLN, INF1N, IW1N/DIL, IW2N/DIR, OW1N, OW2N, SYNCN, RSTN, DEMPR, DEMPL, FSEL1, FSEL2, MUTER, MUTEL,
DITHN, LRCI
3. Pins CKO, DOL, DOR, BCKO, WCKO, DG
NIPPON PRECISION CIRCUITS—5
微控制器 MCU
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