74LVC2G53
2-channel analog multiplexer/demultiplexer
Rev. 05 — 18 June 2008
Product data sheet
1. General description
The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire V
CC
range from 1.65 V to 5.5 V.
2. Features
I
Wide supply voltage range from 1.65 V to 5.5 V
I
Very low ON resistance:
N
7.5
Ω
(typical) at V
CC
= 2.7 V
N
6.5
Ω
(typical) at V
CC
= 3.3 V
N
6
Ω
(typical) at V
CC
= 5 V
I
Switch current capability of 32 mA
I
High noise immunity
I
CMOS low-power consumption
I
TTL interface compatibility at 3.3 V
I
Latch-up performance meets requirements of JESD 78 Class I
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Control inputs accepts voltages up to 5 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74LVC2G53
2-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC2G53DP
−40 °C
to +125
°C
74LVC2G53DC
−40 °C
to +125
°C
74LVC2G53GT
−40 °C
to +125
°C
74LVC2G53GD
−40 °C
to +125
°C
74LVC2G53GM
−40 °C
to +125
°C
TSSOP8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT996-2
SOT902-1
Type number
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
4. Marking
Table 2.
Marking codes
Marking code
V53
V53
V53
V53
V53
Type number
74LVC2G53DC
74LVC2G53DP
74LVC2G53GT
74LVC2G53GD
74LVC2G53GM
5. Functional diagram
Y1
Y0
E
S
Z
001aah795
Fig 1.
Logic symbol
74LVC2G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 18 June 2008
2 of 23
NXP Semiconductors
74LVC2G53
2-channel analog multiplexer/demultiplexer
Y0
S
Z
Y1
E
001aad387
Fig 2.
Logic diagram
6. Pinning information
6.1 Pinning
74LVC2G53
Z
1
8
V
CC
E
2
7
Y0
74LVC2G53
GND
Z
E
GND
GND
1
2
3
4
001aae798
3
6
Y1
8
7
6
5
V
CC
Y0
Y1
S
GND
4
5
S
001aae800
Transparent top view
Fig 3.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT833-1 (XSON8)
74LVC2G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 18 June 2008
3 of 23
NXP Semiconductors
74LVC2G53
2-channel analog multiplexer/demultiplexer
74LVC2G53
terminal 1
index area
Y0
1
V
CC
8
74LVC2G53
Z
E
GND
GND
1
2
3
4
8
7
6
5
V
CC
7
Z
Y1
Y0
Y1
S
S
2
6
E
3
4
5
GND
GND
001aag724
001aai274
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2 (XSON8U)
Fig 6.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT996-2 and
SOT833-1
Z
E
GND
GND
S
Y1
Y0
V
CC
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
common output or input
enable input (active LOW)
ground (0 V)
ground (0 V)
select input
independent input or output
independent input or output
supply voltage
Description
7. Functional description
Table 4.
Input
S
L
H
X
[1]
Function table
[1]
Channel on
E
L
L
H
Y0 to Z or Z to Y0
Y1 to Z or Z to Y1
Z (switch off)
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC2G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 18 June 2008
4 of 23
NXP Semiconductors
74LVC2G53
2-channel analog multiplexer/demultiplexer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
SK
V
SW
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
input clamping current
switch clamping current
switch voltage
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−50
-
[2]
Max
+6.5
+6.5
-
±50
V
CC
+ 0.5
±50
100
-
+150
250
Unit
V
V
mA
mA
V
mA
mA
mA
°C
mW
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
enable and disable mode
V
SW
>
−0.5
V or V
SW
< V
CC
+ 0.5 V
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed.
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
For TSSOP8 packages: above 55
°C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
SW
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
[1]
[2]
[2]
Conditions
Min
1.65
0
Max
5.5
5.5
V
CC
+125
20
10
Unit
V
V
V
°C
ns/V
ns/V
enable and disable mode
[1]
0
−40
-
-
To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
Applies to control signal levels.
[2]
74LVC2G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 18 June 2008
5 of 23
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