74LVC1G58
Low-power configurable multiple function gate
Rev. 04 — 27 April 2009
Product data sheet
1. General description
The 74LVC1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
The three inputs (A, B and C) are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T−
is defined as the
hysteresis voltage V
H
.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V.
±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
I
I
I
I
I
I
I
NXP Semiconductors
74LVC1G58
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G58GW
74LVC1G58GV
74LVC1G58GM
74LVC1G58GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SC-88
TSOP6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1
×
0.5 mm
Version
SOT363
SOT886
SOT891
Type number
plastic surface-mounted package (TSOP6); 6 leads SOT457
4. Marking
Table 2.
Marking
Marking code
[1]
YK
V58
YK
YK
Type number
74LVC1G58GW
74LVC1G58GV
74LVC1G58GM
74LVC1G58GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
4
B
1
Y
A
C
6
001aab687
Fig 1.
Logic symbol
74LVC1G58_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2009
2 of 18
NXP Semiconductors
74LVC1G58
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
74LVC1G58
74LVC1G58
B
GND
1
2
6
5
C
V
CC
A
A
3
001aab686
B
1
6
C
B
GND
74LVC1G58
1
2
3
6
5
4
C
V
CC
Y
GND
2
5
V
CC
3
4
001aab731
Y
A
001aaf956
4
Y
Transparent top view
Transparent top view
Fig 2.
Pin configuration SOT363
(SC-88) and SOT457
(SC-74)
Fig 3.
Pin configuration SOT886
(XSON6)
Fig 4.
Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Inputs
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
H
L
H
H
H
L
L
H = HIGH voltage level; L = LOW voltage level
74LVC1G58_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2009
3 of 18
NXP Semiconductors
74LVC1G58
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 8
see
Figure 6
and
7
see
Figure 6
and
7
see
Figure 8
see
Figure 5
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input NAND
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
2-input OR with both inputs inverted
2-input XOR
Buffer
Inverter
V
CC
B
C
Y
B
1
2
B
C
Y
3
6
5
4
Y
B
C
Y
C
B
C
Y
B
1
2
3
6
5
4
Y
C
V
CC
001aab688
001aab689
Fig 5.
2-input NAND gate or 2-input OR with both
inputs inverted
Fig 6.
2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
V
CC
V
CC
A
C
Y
1
2
A
C
Y
A
3
6
5
4
Y
A
C
Y
A
C
A
C
Y
1
2
3
6
5
4
Y
C
001aab690
001aab691
Fig 7.
2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 8.
2-input OR gate or 2-input NAND gate with
both inputs inverted
V
CC
V
CC
B
B
C
Y
1
2
3
6
5
4
Y
C
A
Y
A
1
2
3
6
5
4
Y
001aab692
001aab693
Fig 9.
2-input XOR gate
Fig 10. Buffer
74LVC1G58_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2009
4 of 18
NXP Semiconductors
74LVC1G58
Low-power configurable multiple function gate
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aab694
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
±50
+6.5
+6.5
±50
100
-
+150
250
Unit
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
−0.5
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For SC-88 and SC-74 packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 package: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
−40
Typ
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
Unit
V
V
V
V
°C
74LVC1G58_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2009
5 of 18
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