74HC154; 74HCT154
4-to-16 line decoder/demultiplexer
Rev. 06 — 12 February 2007
Product data sheet
1. General description
The 74HC154; 74HCT154 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC154; 74HCT154 decoders accept four active HIGH binary address inputs and
provide 16 mutually-exclusive active LOW outputs. The two-input enable gate can be used
to strobe the decoder to eliminate the normal decoding ‘glitches’ on the outputs, or can be
used for the expansion of the decoder.
The enable gate has two ANDed inputs which must be LOW to enable the outputs.
The 74HC154; 74HCT154 can be used as a 1-to-16 demultiplexer by using one of the
enable inputs as the multiplexed data input.
When the other enable input is LOW, the addressed output will follow the state of the
applied data.
2. Features
I
I
I
I
I
16-line demultiplexing capability
Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
Complies with JEDEC standard no. 7A
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
ESD protection:
N
HBM EIA/JESD22-A114D exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC154
74HC154N
74HC154D
74HC154DB
74HC154PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP24
SO24
SSOP24
TSSOP24
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width
7.5 mm
SOT101-1
SOT137-1
Description
Version
Type number
plastic shrink small outline package; 24 leads; body width SOT340-1
5.3 mm
plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
SOT355-1
NXP Semiconductors
74HC154; 74HCT154
4-to-16 line decoder/demultiplexer
Table 1.
Ordering information
…continued
Package
Temperature range Name
Description
Version
−40 °C
to +125
°C
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin SOT815-1
quad flat package; no leads; 24 terminals; body
3.5
×
5.5
×
0.85 mm
DIP24
SO24
SSOP24
TSSOP24
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width
7.5 mm
SOT101-1
SOT137-1
Type number
74HC154BQ
74HCT154
74HCT154N
74HCT154D
−40 °C
to +125
°C
−40 °C
to +125
°C
74HCT154DB
−40 °C
to +125
°C
74HCT154PW
−40 °C
to +125
°C
74HCT154BQ
−40 °C
to +125
°C
plastic shrink small outline package; 24 leads; body width SOT340-1
5.3 mm
plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
SOT355-1
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin SOT815-1
quad flat package; no leads; 24 terminals; body
3.5
×
5.5
×
0.85 mm
4. Functional diagram
23
22
21
20
A0
A1
A2
A3
18
19
E0
DECODER
E1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10 Y11 Y12 Y13 Y14 Y15
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
001aab071
Fig 1. Functional diagram
74HC_HCT154_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 12 February 2007
2 of 21
NXP Semiconductors
74HC154; 74HCT154
4-to-16 line decoder/demultiplexer
DX
23
22
G
21
20
3
0
0
15
0
1
2
3
4
5
6
7
23
A0
Y0
Y1
22
A1
1
2
8
9
10
11
12
20
18
19
E0
E1
A3
Y14
Y15
16
17
&
18
19
EN
14
15
16
17
18
19
13
1
2
3
4
5
6
7
8
9
10
11
13
14
15
&
23
22
21
20
1
2
4
8
X/Y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
EN
14
15
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
21
A2
001aab069
001aab070
Fig 2. Logic symbol
Fig 3. IEC logic symbol
E0
E1
A0
A1
A2
A3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
001aab072
Fig 4. Logic diagram
74HC_HCT154_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 12 February 2007
3 of 21
NXP Semiconductors
74HC154; 74HCT154
4-to-16 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
74HC154BQ
74HCT154BQ
terminal 1
index area
Y1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
2
3
4
5
6
7
8
9
24 V
CC
23 A0
22 A1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
2
3
4
5
6
7
8
9
V
CC
GND 12
(1)
24 V
CC
23 A0
22 A1
21 A2
20 A3
19 E1
18 E0
17 Y15
16 Y14
15 Y13
14 Y12
Y11 13
74HC154D
74HCT154D
74HC154DB
74HCT154DB
74HC154N
74HCT154N
74HC154PW
74HCT154PW
21 A2
20 A3
19 E1
18 E0
17 Y15
16 Y14
15 Y13
14 Y12
13 Y11
Y9 10
Y10 11
Y9 10
Y10 11
GND 12
001aab067
1
Y0
001aab068
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
a supply pin or input.
Fig 5. Pin configuration for SO24, DIP24, SSOP24 and
TSSOP24
Fig 6. Pin configuration for DHVQFN24
5.2 Pin description
Table 2.
Symbol
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
GND
Y11
Y12
74HC_HCT154_6
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
data output (active LOW)
ground (0 V)
data output (active LOW)
data output (active LOW)
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 12 February 2007
4 of 21
NXP Semiconductors
74HC154; 74HCT154
4-to-16 line decoder/demultiplexer
Table 2.
Symbol
Y13
Y14
Y15
E0
E1
A3
A2
A1
A0
V
CC
Pin description
…continued
Pin
15
16
17
18
19
20
21
22
23
24
Description
data output (active LOW)
data output (active LOW)
data output (active LOW)
enable input (active LOW)
enable input (active LOW)
address input
address input
address input
address input
supply voltage
6. Functional description
Table 3.
Input
H
H
L
L
H
L
H
L
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
[1]
Function table
[1]
Output
Y6
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
Y7
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
Y8
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
Y9
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
Y10 Y11 Y12 Y13 Y14 Y15
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
E0 E1 A0 A1 A2 A3 Y0 Y1 Y2 Y3 Y4 Y5
H = HIGH voltage level
L = LOW voltage level
X = don’t care.
74HC_HCT154_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 12 February 2007
5 of 21
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