74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 7 — 18 January 2013
Product data sheet
1. General description
The 74LVCH16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring
separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state
outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable
(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices.
When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of
these devices in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the
latches are transparent, that is, the latch outputs change each time its corresponding
D-input changes. The latches store the information that was present at the D-inputs one
set-up time (t
su
) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs. When OE is HIGH, the outputs
go to the high impedance OFF-state. Operation of the OE input does not affect the state of
the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors
to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
High-impedance when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC16373ADGG
74LVCH16373ADGG
74LVC16373ADL
74LVCH16373ADL
40 C
to +125
C
SSOP48
40 C
to +125
C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic shrink small outline package; 48 leads;
body width 7.5 mm
Version
SOT362-1
SOT370-1
Type number
4. Functional diagram
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mgu770
1
24
1OE
1LE
1EN
C3
2EN
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1LE
48
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2LE
25
mgu768
2OE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2LE
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 18 January 2013
2 of 17
NXP Semiconductors
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH
1
LE
LE
LATCH
9
LE
LE
1LE
1OE
to 7 other channels
2LE
2OE
to 7 other channels
mgu769
Fig 3.
Logic diagram
V
CC
data input
to internal circuit
mgu771
Fig 4.
Bus hold circuit
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 18 January 2013
3 of 17
NXP Semiconductors
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48
1LE
47
1D0
46
1D1
45
GND
44
1D2
43
1D3
42
V
CC
41
1D4
40
1D5
39
GND
38
1D6
37
1D7
36
2D0
35
2D1
34
GND
33
2D2
32
2D3
31
V
CC
30
2D4
29
2D5
28
GND
27
2D6
26
2D7
25
2LE
001aad112
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
2Q2
16
2Q3
17
V
CC
18
2Q4
19
2Q5
20
GND
21
2Q6
22
2Q7
23
2OE
24
16373A
Fig 5.
Pin configuration SSOP48 and TSSOP48
5.2 Pin description
Table 2.
Symbol
1OE
2OE
1LE
2LE
GND
V
CC
1Q[0:7]
2Q[0:7]
1D[0:7]
2D[0:7]
Pin description
Pin
1
24
48
25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
Description
output enable input (active LOW)
output enable input (active LOW)
latch enable input (active HIGH)
latch enable input (active HIGH)
ground (0 V)
supply voltage
data output
data output
data input
data input
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 18 January 2013
4 of 17
NXP Semiconductors
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3.
Function table
Per section of eight bits
[1]
.
Operating modes
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
Input
nOE
L
L
L
L
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
Internal latch
nLE
H
H
L
L
L
L
nDn
L
H
l
h
l
h
L
H
L
H
L
H
Output
nQ0 to nQ7
L
H
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
Above 60
C,
the value of P
tot
derates linearly with 5.5 mW/K.
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 18 January 2013
5 of 17
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