THIS SPEC IS OBSOLETE
Spec No:
001-00439
Spec Title:
CY7C1517KV18/CY7C1528KV18/CY7C1519KV18/
CY7C1521KV18, 72-MBIT DDR-II SRAM 4-WORD
BURST ARCHITECTURE
Sunset Owner: Jayasree Nayar
(NJY)
Replaced by:
None
CY7C1517KV18, CY7C1528KV18
CY7C1519KV18, CY7C1521KV18
72-Mbit DDR II SRAM 4-Word
Burst Architecture
Features
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Functional Description
The CY7C1517KV18, CY7C1528KV18, CY7C1519KV18, and
CY7C1521KV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with four 8-bit words in the case of CY7C1517KV18
and four 9-bit words in the case of CY7C1528KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘00’ internally in the case of CY7C1517KV18 and
CY7C1528KV18. For CY7C1519KV18 and CY7C1521KV18,
the burst counter takes in the least two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1519KV18, and four 36-bit words in the case of
CY7C1521KV18, sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
72-Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
333 MHz Clock for High Bandwidth
4-word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Synchronous Internally Self-timed Writes
DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
1.8V Core Power Supply with HSTL Inputs and Outputs
Variable drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V–V
DD
)
❐
Supports both 1.5V and 1.8V IO supply
Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase Locked Loop (PLL) for accurate Data Placement
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Configurations
CY7C1517KV18 – 8M x 8
CY7C1528KV18 – 8M x 9
CY7C1519KV18 – 4M x 18
CY7C1521KV18 – 2M x 36
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
333 MHz
300
410
410
420
510
300 MHz
300
390
390
400
470
250 MHz
250
350
350
360
420
200 MHz
200
310
310
320
370
167 MHz
167
290
290
290
330
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-00439 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 15, 2011
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CY7C1517KV18, CY7C1528KV18
CY7C1519KV18, CY7C1521KV18
Logic Block Diagram (CY7C1517KV18)
A
(20:0)
LD
K
K
DOFF
21
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
8
2M x 8 Array
2M x 8 Array
2M x 8 Array
2M x 8 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
8
8
8
8
8
CQ
CQ
DQ
[7:0]
Read Data Reg.
32
Control
Logic
V
REF
R/W
NWS
[1:0]
16
16
Reg.
Reg.
Reg.
Logic Block Diagram (CY7C1528KV18)
A
(20:0)
LD
K
K
DOFF
21
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
9
2M x 9 Array
2M x 9 Array
2M x 9 Array
2M x 9 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
9
9
9
9
9
CQ
CQ
DQ
[8:0]
Read Data Reg.
36
Control
Logic
V
REF
R/W
BWS
[0]
18
18
Reg.
Reg.
Reg.
Document Number: 001-00439 Rev. *G
Page 2 of 33
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CY7C1517KV18, CY7C1528KV18
CY7C1519KV18, CY7C1521KV18
Logic Block Diagram (CY7C1519KV18)
A
(1:0)
2
A
(22:0)
22
LD
K
K
DOFF
20
Burst
Logic
Write Add. Decode
Read Add. Decode
A
(22:2)
Address
Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
18
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
18
18
18
18
18
CQ
CQ
DQ
[17:0]
Read Data Reg.
72
Control
Logic
V
REF
R/W
BWS
[1:0]
36
36
Reg.
Reg.
Reg.
Logic Block Diagram (CY7C1521KV18)
A
(1:0)
2
A
(20:0)
21
LD
K
K
DOFF
19
Burst
Logic
Write Add. Decode
Read Add. Decode
A
(20:2)
Address
Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
512K x 36 Array
512K x 36 Array
512K x 36 Array
512K x 36 Array
36
CLK
Gen.
Output
Logic
Control
R/W
C
C
36
36
36
36
36
CQ
CQ
DQ
[35:0]
Read Data Reg.
144
Control
Logic
V
REF
R/W
BWS
[3:0]
72
72
Reg.
Reg.
Reg.
Document Number: 001-00439 Rev. *G
Page 3 of 33
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CY7C1517KV18, CY7C1528KV18
CY7C1519KV18, CY7C1521KV18
Contents
Features ............................................................................ 1
Configurations .................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram (CY7C1517KV18).......................... 2
Logic Block Diagram (CY7C1528KV18).......................... 2
Logic Block Diagram (CY7C1519KV18)........................... 3
Logic Block Diagram (CY7C1521KV18).......................... 3
Contents ............................................................................ 4
Pin Configuration ............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout ................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
DDR Operation.......................................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Application Example ...................................................... 11
Truth Table ...................................................................... 11
Burst Address Table
(CY7C1519KV18, CY7C1521KV18) ................................ 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO)................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram....................................... 16
TAP Controller Block Diagram...................................... 17
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in DDR II SRAM ........................... 21
Power Up Sequence ................................................. 21
PLL Constraints......................................................... 21
Maximum Ratings........................................................... 22
Operating Range ............................................................ 22
Electrical Characteristics .............................................. 22
DC Electrical Characteristics..................................... 22
AC Electrical Characteristics..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ....................................................... 24
Switching Characteristics ............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ..................................................... 28
Package Diagram ........................................................... 31
Document History Page................................................. 32
Sales, Solutions, and Legal Information ....................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Document Number: 001-00439 Rev. *G
Page 4 of 33
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