Product Description, Revision 6
May 11, 2006
TMXL84622
Ultramapper
™
Lite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
1 Introduction
The documentation package for the TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
system chip consists of the following documents:
The
Ultramapper
Family Register Description and the
Ultramapper
Family System Design Guide. These documents are
available on a password protected website.
The
UltramapperLite
Product Description (this document) and the
UltramapperLite
Hardware Design Guide. These doc-
uments are available on the public website shown below.
To contact Agere, please see the last page of this document.
To access related documents, including the documents mentioned above, please go to the following public website, or
contact your Agere representative:
http://www.agere.com/telecom/mappers_muxes.html
622/155 Mbits/s SONET/SDH
ADM Front End
LOPOH
6
DS3/E3/DS2/DS1/E1 PDH
Tributary Termination
High-Speed IF
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
LOPOH
FRM
(X3)
x28/x21
DS1/J1/E1
TPG/TPM
CG
5
PLL IF
CDR
TMUX
STSPP
Clock/Sync
6
SPEMPR
(x3)
(3-5)
S
T
S
X
C
System Interfaces
42
Protection Link
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
STS-12/
STM-4/
STS-3/
STM-1
CDR
MRXC
SPEMPR
(x3)
(0-2)
(x3)
x28/x21
VTMPR
3
1
(x6) DS3/E3
(x3) STS-1
(x3) NSMI
(x3) STS-1
(Total of 3 STS-1 Max)
DS1/J1/E1
VT/TU
DS2/E2
DS3/E3
24
180
STS-1
LT
Low-Speed I/O
Miscellaneous
24
6
(x3)
(x3)
(x3)
E13
M13
MUX
MUX
3
1
Transport Modes
4DS1/J1/E1
(x30): x28/x21 + prot.
4DS2/E2
(X30): x21/x12 + prot.
4VT/TU
(X30): x28/x21 + prot.
JTAG
5
MPU
49
MCDR
6
12
1
1
X3
x28/x21
DS1/E1
x6
DS3/E3
DJA
6
2
6
DJA
Power and GND pins not shown
2
JTAG IF
(x3) (x3)
(x3)
MPU IF
STS-3/STM-1 Mate DS3/E3 PLL IF
(Optional)
Interconnect
E2,
DS2,
VC12 VC11
AIS Clocks
DS1XCLK,
E1XCLK
TOAC POAC
DS3XCLK,
E3XCLK
Figure 1-1.
UltramapperLite
Block Diagram and High-Level Interface Definition
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Table of Contents
Contents
Product Description, Revision 6
May 11, 2006
Page
1 Introduction .........................................................................................................................................................................1
2 Features .............................................................................................................................................................................4
2.1 TMUX and CDR (x1) ...................................................................................................................................................4
2.2 CDR .............................................................................................................................................................................4
2.3 STS-12 Pointer Processor (STSPP) (x1) ....................................................................................................................4
2.4 STS Cross Connect (STSXC) (x1) ..............................................................................................................................5
2.5 Mate Clock and Data Recovery (MCDR) (x1) ..............................................................................................................5
2.6 STS-1 Line Terminating (STS1LT) (x3) .......................................................................................................................5
2.7 Synchronous Payload Envelope Mapper (SPEMPR) (x6) ...........................................................................................5
2.8 Test Pattern Generator/Monitor (TPG/TPM) (x1) ........................................................................................................6
2.9 Virtual Tributary Mapper (VTMPR) (x3) .......................................................................................................................6
2.10 M13/E13 MUX (x3) ....................................................................................................................................................6
2.10.1 M13 ..................................................................................................................................................................6
2.10.2 E13 ...................................................................................................................................................................7
2.11 DS1/J1/E1 Framing (FRM) (3x28/21) ........................................................................................................................7
2.12 STS-1/DS3/E3/DS2/E2/DS1/E1/VT/TU Multirate Cross Connect (MRXC) (x1) ........................................................7
2.13 DS1/E1 Digital Jitter Attenuation (DJA) (3x28/21) .....................................................................................................8
2.14 DS3/E3 Digital Jitter Attenuation (DJA) (x1) ..............................................................................................................8
2.15 Microprocessor Unit (MPU) (x1) ................................................................................................................................8
2.16 JTAG .........................................................................................................................................................................8
3 Overview .............................................................................................................................................................................9
4 Application Diagrams ........................................................................................................................................................10
4.1 STS-12/STM-4 1 + 1 Four Device Application ...........................................................................................................10
4.2 STS-3/STM-1 to/from DS3/E3 Application ................................................................................................................11
4.3 UPSR HO/LO Application with DRI ...........................................................................................................................12
4.4 STS-12/STM-4 Transport (Mixed DS3/E3 and DS1/E1) Application .........................................................................13
4.5 Transport Unprotected Add/Drop Ring Application ...................................................................................................14
4.6 STS-12/STM-4 to/from DS3/E3 TransMUX Application ............................................................................................15
4.7 Portless TransMUX Application .................................................................................................................................16
4.8 STS-12/STM-4 to/from DS3/E3 Application ..............................................................................................................17
4.9 Data NSMI Application ..............................................................................................................................................18
5 Block Description ..............................................................................................................................................................19
5.1 TMUX/Clock and Data Recovery (CDR) ...................................................................................................................19
5.1.1 Transmit Path Section/Line Overhead .............................................................................................................19
5.1.2 Receive Path Section/Line Overhead ..............................................................................................................19
5.1.3 Pointer Interpreter ............................................................................................................................................20
5.1.4 Path Termination Function ...............................................................................................................................20
5.2 STS-12/STM-4 Pointer Processor (STSPP) ..............................................................................................................20
5.3 STS-1 Line Terminating (STS1LT) ............................................................................................................................20
5.4 STS Cross Connect (STSXC) ...................................................................................................................................20
5.5 Mate Interconnect and Clock Data Recovery (MCDR) ..............................................................................................20
5.6 SPE/AU-3 Mapper (SPEMPR) ..................................................................................................................................21
5.7 VT/TU Mapper (VTMPR) ...........................................................................................................................................21
5.7.1 Receive Direction .............................................................................................................................................21
5.7.2 Transmit Direction ............................................................................................................................................21
5.8 M13/E13 Multiplexer (M13/E13 MUX) .......................................................................................................................22
5.8.1 M13 MUX .........................................................................................................................................................22
5.8.1.1 Receive Direction ..................................................................................................................................22
5.8.1.2 Transmit Direction .................................................................................................................................22
5.8.2 E13 MUX ..........................................................................................................................................................22
5.9 Multirate Cross Connect (MRXC) ..............................................................................................................................23
5.10 DS1 Digital Jitter Attenuator (DS1/E1 DJA) .............................................................................................................23
2
Agere Systems Inc.
Product Description, Revision 6
May 11, 2006
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Table of Contents
(continued)
Contents
Page
5.11 DS3 Digital Jitter Attenuator (DS3/E3 DJA) .............................................................................................................24
5.12 Test Pattern Generator/Monitor (TPG/TPM) ...........................................................................................................24
5.13 Low-Order Path Over Head .....................................................................................................................................24
5.14 Framer (FRM) ..........................................................................................................................................................24
5.14.1 Line Decoder/Encoder ...................................................................................................................................24
5.14.2 Receive Frame Aligner/Transmit Frame Formatter ........................................................................................24
5.14.3 Receive Performance Monitor ........................................................................................................................25
5.14.4 Signaling Processor .......................................................................................................................................25
5.14.5 Facility Data Link (FDL) Processor ................................................................................................................25
5.14.6 HDLC Unit ......................................................................................................................................................26
6 Glossary ...........................................................................................................................................................................27
Figures
Page
Figure 1-1. UltramapperLite Block Diagram and High-Level Interface Definition ...................................................................1
Figure 4-1. STS-12/STM-4 1 + 1 Four Device Configuration ...............................................................................................10
Figure 4-2. STS-3/STM-1 to/from 3 x DS3s/E3s Configuration............................................................................................11
Figure 4-3. UPSR HO/LO with DRI Configuration ................................................................................................................12
Figure 4-4. 56 DS1s/42 E1s Plus 10 DS3s/E3s Mapped and Multiplexed to/from an STS-12/STM-4.................................13
Figure 4-5. Up to Three EC-1s, Plus Three DS3s/E3s, Plus 28 DS1s/21 E1s Add/Dropped from an OC-12 Ring .............14
Figure 4-6. 12 x DS3s/E3s Transmultiplexed to/from a VT-Mapped STS-12/STM-4 ...........................................................15
Figure 4-7. Portless TransMUX Application .........................................................................................................................16
Figure 4-8. Two Device Termination of an STS-12/STM-4 ..................................................................................................17
Figure 4-9. NSMI Slipless Clear Channel Data Transport Configuration .............................................................................18
Agere Systems Inc.
3
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Product Description, Revision 6
May 11, 2006
Multiplexes/demultiplexes three VC-3 signals to/from an
SDH STM-1 (AU-4) signal via a TUG-3 construction.
Provides STS-1-only mode for receive and transmit
directions.
Provides separate protection input for support of 1:1
and 1 + 1.
Provides SONET/SDH loss-of-signal (LOS), out-of-frame
(OOF), loss-of-frame (LOF), and loss-of-clock (LOC)
detection.
Provides STS-12/STM-4/STS-3/STM-1/STS-1 selectable
scrambler/descrambler functions.
Provides B1/B2/B3 generation/detection for STS-12/
STM-4/STS-3/STM-1/STS-1.
Provides STS-12/STM-4/STS-3/STM-1/STS-1 pointer
interpretation.
Complies with GR-253-CORE, T1.105, G.707 (March
1996), G.783, G.806, G.821, and ETSI 417-1-1.
2 Features
Versatile IC supports SONET/SDH 622.08/
155.52 Mbits/s interface solutions for DS3/E3, DS2/E2,
and DS1/J1/E1 applications.
Terminates up to 28 DS1/J1 or 21 E1 framed signals. All
popular framing formats are supported.
Terminates up to six DS3/E3, 21 DS2, or 12 E2
channelized or unchannelized signals with grooming for
channelized DS3/E3/DS2/E2.
Mates with up to three other
UltramapperLites
to provide
112/84 DS1/J1/E1 terminations.
Terminated DS3/E3, DS2/E2, DS1/J1/E1 signals may be
flexibly mapped into the SONET/SDH interface using all
allowed MUXing structures.
Supports 1:1, 1 + 1, and 1:N (DS2/DS1/E1) protection
schemes with dedicated interfaces.
3.3 V I/O, 1.5 V CORE, low power (<3 W) and –40
°
C to
+85
°
C temperature range allows for uncontrolled or con-
vection cooled environments.
Built-in clock and data recovery circuits with optional
input for forward clocking of STS-3 input.
Full SONET/SDH compliant alarm reporting.
Supports full processing for all line/section/path over-
head with inhibitable automatic generation of AIS, RDI,
REI, and N times filtering on critical overhead.
Allows extraction/insertion of DCC-L, DCC-S, or up to
20 Mbits/s using specified overhead bytes for the data
communications channel.
Provides full high-speed pointer processing and synchro-
nization of the 8 kHz frame/2 kHz superframe to the sys-
tem timing.
Loopbacks, manual error insertion, internal pattern
generator/monitor, and internal cross connects simplify
debugging and diagnostics.
Standard 700-pin ball grid array (PBGA).
Complies with all appropriate
Telcordia
®
,
ITU
™
,
ANSI
®
,
ETSI, and Japanese TTC standards as noted.
2.2 CDR
Receives data at STS-12/STM-4 (622.08 Mbits/s) or
STS-3/STM-1 (155.52 MHz) data rate.
155.52 MHz/622.08 MHz ± 20 ppm input reference clock
for on-chip PLL.
Meets type B jitter tolerance specification of
ITU-T
recommendation G.783.
No output clock drift in absence of data transitions once
lock is acquired.
2.3 STS-12 Pointer Processor (STSPP) (x1)
SONET and SDH compliant.
Configurable STS-3/STM-1 or STS-12/STM-4 mode.
2.1 TMUX and CDR (x1)
Multiplexes/demultiplexes twelve STS-1 signals or four
STS-3c signals to/from a SONET STS-12 signal.
Multiplexes three STS-1 signals into a SONET
STS-3 signal.
Multiplexes/demultiplexes four STM-1 (AU-4 or 3xAU-3)
signals to/from an SDH STM-4 signal.
Multiplexes/demultiplexes three VC-3 signals to/from an
SDH STM-1 (3xAU-3) signal.
Supports an arbitrary mix of STS-1 and STS-3c
tributaries, and SDH equivalents for passthrough from
receiver to transmitter.
Supports STS-n add/drop capability.
Complies with GR-253-CORE, T1.105, G.707 (March
1996), G.783, G.806, G.821, and ETSI 417-1-1.
4
Agere Systems Inc.
Product Description, Revision 6
May 11, 2006
2.4 STS Cross Connect (STSXC) (x1)
Internal clocks and controls are user transparent.
30 x 30 STS-1 strictly nonblocking cross connect.
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
2.7 Synchronous Payload Envelope Mapper
(SPEMPR) (x6)
The SPE mapper accepts/delivers TUG-2 data from/to
the VT mapper. The TUG-2 data is mapped/demapped
either to/from an AU-3/STS-1 signal for the North Ameri-
can digital systems or to/from a TUG-3 signal for the
ITU-
based systems. Only available for SPEMPR 0—2.
The SPE mapper accepts/delivers channelized DS3 data
from/to the M13 MUX/deMUX. The DS3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for the
North American digital systems or to/from a TUG-3 signal
for the
ITU-based
systems. Only available for
SPEMPR 3—5.
The SPE mapper accepts/delivers channelized or
unchannelized DS3 signals at a 44.736 Mbits/s rate from
external I/O. The DS3 signals are mapped/demapped
the same way as the M13 signal described above.
The SPE mapper accepts/delivers channelized E3 data
from/to the E13 MUX/deMUX. The E3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for the
North American digital systems or to/from a TUG-3 signal
for the
ITU-based
systems. Only available for
SPEMPR 3—5.
The SPE mapper accepts/delivers channelized or
unchannelized E3 signals at a 34.368 Mbits/s rate from
external I/O. These E3 signals are mapped/demapped
the same way as the E13 signal described above.
The SPE mapper has a DS3/E3 loopback circuit placed
to demap and remap a DS3/E3 signal. It is particularly
useful in cases where a DS3/E3 signal, mapped as an
AU-3/STS-1 signal, requires remapping as a TUG-3 sig-
nal or vice versa.
The SPE mapper supports a path overhead access
channel (POAC). Seven path overhead bytes (J1, C2,
F2, H4, F3, K3, and N1) can be inserted/dropped through
this channel. This channel works as the master, meaning
it provides a clock in both the transmit and receive direc-
tions and POH data can be inserted on the transmit side
or dropped on the receive side.
Path overhead byte B3 (BIP error) generation/detection
and programmable BIP-8 bit error rate insertion.
Signal fail and signal degrade indicators available to
report bit error rates above standard provisionable
thresholds.
Capable of detecting/inserting AIS, RDI, and REI.
Monitoring is provided on all the TUG-3 path overhead
bytes.
N1 tandem connection support is provided.
TUG-3 pointer processor supports add/drop multiplexing.
5
The following STSXC outputs may be sourced from the
subsequent list of inputs without restriction per
STS-1/STM-0.
Number of STS-1s
12
6
3
9
Number of STS-1s
12
6
3
9
Output Block
TMUX
SPEMPR
STS1LT or STS1LT PP
Mate CDR (from TMUX only)
Input Block
TMUX or STS-12PP
SPEMPR
STS1LT
Mate CDR (to TMUX only)
2.5 Mate Clock and Data Recovery (MCDR) (x1)
Provides glueless capability to connect
UltramapperLites
in a master/slave configuration.
Loss-of-clock detection from the three external
155.52 MHz clock inputs.
Loss-of-frame (LOF), out-of-frame (OOF), and B2 error
detection on the three 155.52 Mbits/s interfaces. Also
RDI and REI monitoring and generation is available.
Manual B2 error insertion for debugging.
Provisionable delay between output data frame and
8 kHz sync to accommodate variable length paths to
slave
UltramapperLites.
2.6 STS-1 Line Terminating (STS1LT) (x3)
Supports standard SPE mappings for sub-STS-1 pay-
loads (VT-mapped: 28 DS1, 28 J1, or 21 E1 signals).
Supports standard SPE mappings for STS-1 payloads
(DS3/E3).
Detects STS-1 loss-of-signal (LOS), out-of-frame (OOF),
loss-of-frame (LOF), AIS-P, and LOP conditions.
Provides STS-1 selectable scrambler/descrambler func-
tions and B1/B2/B3 generation/detection.
Provides STS-1 pointer interpretation/processing.
Complies with GR-253-CORE, T1.105, G.707 (March
1996), G.783, G.826, G.821, and ETSI 417-1-1.
Agere Systems Inc.
Microchip MCU
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