HY62V256B-(I)/HY62U256B-(I) Series
32Kx8bit CMOS SRAM
DESCRIPTION
The HY62V256B-(I)/ HY62U256B-(I) is a high-
speed, low power and 32,786 x 8-bits CMOS
Static Random Access Memory fabricated using
Hyundai's high performance CMOS process
technology. It is suitable for use in low voltage
operation and battery back-up application. This
device has a data retention mode that guarantees
data to remain valid at the minimum power supply
voltage of 2.0 volt.
FEATURES
•
•
•
•
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Low power consumption
Battery backup(LL-part)
- 2.0V(min.) data retention
•
Standard pin configuration
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Product
Voltage
Speed
Operation
Standby
No.
(V)
(ns)
Current(mA)
Current(uA)
HY62V256B
3.3
85/100/120
2
20
HY62V256B-I
3.3
85/100/120
2
25
HY62U256B
3.0
100/120/150
2
15
HY62U256B-I
3.0
100/120/150
2
20
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
Vcc
/WE
A13
A8
A9
A11
/OE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A1
A0
I/O1
I/O2
I/O3
Vss
I/O4
I/O5
I/O6
I/O7
I/O8
/CS
A10
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A14
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Inputs
Data Input/Output
Power(+3.3V or 3.0V)
Ground
A0
BLOCK DIAGRAM
SENSE AMP
ROW DECODER
ADD INPUT BUFFER
I/O1
OUTPUT BUFFER
I/O8
COLUMN DECODER
A14
/CS
/OE
/WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jan.99
Hyundai Semiconductor
CONTROL
LOGIC
WRITE DRIVER
MEMORY ARRAY
512x512
HY62V256B-(I)/HY62U256B-(I) Series
ORDERING INFORMATION
Part No.
HY62V256BLLJ
HY62V256BLLT1
HY62V256BLLR1
HY62V256BLLJ-I
HY62V256BLLT1-I
HY62V256BLLR1-I
HY62U256BLLJ
HY62U256BLLT1
HY62U256BLLR1
HY62U256BLLJ-I
HY62U256BLLT1-I
HY62U256BLLR1-I
Speed
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
Temp.
Package
SOP
TSOP-I Standard
TSOP-I Reversed
SOP
TSOP-I Standard
TSOP-I Reversed
SOP
TSOP-I Standard
TSOP-I Reversed
SOP
TSOP-I Standard
TSOP-I Reversed
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, V
IN,
V
OUT
T
A
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
Rating
-0.5 to 4.6
0 to 70
-40 to 85
T
STG
P
D
I
OUT
T
SOLDER
Storage Temperature
Power Dissipation
Data Output Current
Lead Soldering Temperature & Time
-65 to 150
1.0
50
260
•
10
Unit
V
°C
°C
Remark
HY62V256B
HY62U256B
HY62V256B-I
HY62U256B-I
W
mA
°C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
T
A
=0°C to 70°C (Normal)/ -40°C to 85°C(E.T.)
Symbol
Parameter
Product
Vcc
Power Supply Voltage
HY62V256B-(I)
HY62U256B-(I)
V
SS
Ground
V
IH
Input High Voltage
V
IL
Input Low Voltage
Min.
3.0
2.7
0
2.2
-0.5
(2)
Type
3.3
3.0
0
-
-
Max.
3.6
3.3
(1)
0
Vcc+0.3
0.4
Unit
V
V
V
V
V
Note
1. The maximum value of HY62U256B-(I) part is 3.6V at 100ns.
2. V
IL
= -3.0V for pulse width less than 30ns.
Rev.02 /Jan.99
2
HY62V256B-(I)/HY62U256B-(I) Series
TRUTH TABLE
/CS
H
L
L
L
/WE
X
H
H
L
/OE
X
H
L
X
MODE
Standby
Output Disabled
Read
Write
I/O OPERATION
High-Z
High-Z
Data Out
Data In
Note
1. H=V
IH
, L=V
IL
, X=Don't Care
DC CHARACTERISTICS
Vcc = 3.3V
±10%/3.0V ±10%,
T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ. Max.
Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
-1
-
1
uA
/
OE
=
V
IH
or /WE = V
IL
Icc
Operating Power Supply
/CS = V
IL
,
-
1
2
mA
Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
I
CC1
Average Operating Current
/CS = V
IL,
-
15
30
mA
Min. Duty Cycle = 100%, I
I/O =
0mA
I
SB
TTL Standby Current
/CS= V
IH
-
-
0.3
mA
(TTL Inputs)
I
SB1
CMOS
HY62V256B
/CS > Vcc - 0.2V
LL
-
1.5
20
uA
Standby HY62V256B-I
LL
-
1.5
25
uA
Current
HY62U256B
LL
-
1
15
uA
HY62U256B-I
LL
-
1
20
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1mA
2.2
-
-
V
Note : Typical values are at Vcc =3.3V/3.0V, T
A
= 25°C
Rev.02 /Jan.99
3
HY62V256B-(I)/HY62U256B-(I) Series
AC CHARACTERISTICS(I)
Vcc = 3.3V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise specified.
-85
-10
-12
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
TRC
Read Cycle Time
85
-
100
-
120
-
2
TAA
Address Access Time
-
85
-
100
-
120
3
TACS
Chip Select Access Time
-
85
-
100
-
120
4
TOE
Output Enable to Output Valid
-
45
-
50
-
60
5
TCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
6
TOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
7
TCHZ
Chip Disable to Output in High Z
0
30
0
30
0
40
8
TOHZ Out Disable to Output in High Z
0
30
0
30
0
40
9
TOH
Output Hold from Address Change
10
-
10
-
10
-
WRITE CYCLE
10 TWC
Write Cycle Time
85
-
100
-
120
-
11 TCW
Chip Selection to End of Write
70
-
80
-
100
-
12 TAW
Address Valid to End of Write
70
-
80
-
100
-
13 TAS
Address Set-up Time
0
-
0
-
0
-
14 TWP
Write Pulse Width
55
-
60
-
85
-
15 TWR
Write Recovery Time
0
-
0
-
0
-
16 TWHZ Write to Output in High Z
0
30
0
30
0
30
17 TDW
Data to Write Time Overlap
40
-
45
-
50
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
5
-
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS(II)
Vcc = 3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise specified.
-10
-12
-15
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
TRC
Read Cycle Time
100
-
120
-
150
-
2
TAA
Address Access Time
-
100
-
120
-
150
3
TACS
Chip Select Access Time
-
100
-
120
-
150
4
TOE
Output Enable to Output Valid
-
50
-
60
-
75
5
tCLZ
Chip Select to Output in Low Z
20
-
20
-
20
-
6
tOLZ
Output Enable to Output in Low Z
10
-
10
-
10
-
7
tCHZ
Chip Disable to Output in High Z
0
30
0
40
0
50
8
tOHZ
Out Disable to Output in High Z
0
30
0
40
0
50
9
tOH
Output Hold from Address Change
20
-
20
-
20
-
WRITE CYCLE
10 tWC
Write Cycle Time
100
-
120
-
150
-
11 tCW
Chip Selection to End of Write
80
-
100
-
120
-
12 tAW
Address Valid to End of Write
80
-
100
-
120
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
75
-
85
-
100
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
35
0
40
0
50
17 tDW
Data to Write Time Overlap
45
-
50
-
60
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
10
-
10
-
20
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.02 /Jan.99
4
HY62V256B-(I)/HY62U256B-(I) Series
AC TEST CONDITIONS
T
A
= 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified
PARAMETER
VALUE
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
T
A
= 25°C, f = 1.0MHz
Symbol
Parameter
C
IN
Input Capacitance
C
I/O
Input /Output Capacitance
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
6
8
Unit
pF
pF
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
tAA
OE
tOE
tOLZ
CS
tACS
tCLZ
Data
Out
High-Z
Data Valid
tOHZ
tCHZ
tOH
Rev.02 /Jan.99
5
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