Datasheet> 器件分类 > 存储> 存储> MT45W256KW16BEGB-708IT

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MT45W256KW16BEGB-708IT: 产品描述Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 1 MM HEIGHT 0.75 MM PITCH, GREEN, VFBGA-54; 产品类别存储存储; 文件大小2MB，共58页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT45W256KW16BEGB-708IT概述

Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 1 MM HEIGHT 0.75 MM PITCH, GREEN, VFBGA-54

MT45W256KW16BEGB-708IT规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
零件包装代码	BGA
包装说明	VFBGA, BGA54,6X9,30
针数	54
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	70 ns
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B54
JESD-609代码	e1
长度	8 mm
内存密度	4194304 bit
内存集成电路类型	PSEUDO STATIC RAM
内存宽度	16
功能数量	1
端子数量	54
字数	262144 words
字数代码	256000
工作模式	ASYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256KX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装等效代码	BGA54,6X9,30
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	1.8,1.8/3.3 V
认证状态	Not Qualified
座面最大高度	1 mm
最大待机电流	0.00001 A
最大压摆率	0.035 mA
最大供电电压 (Vsup)	1.95 V
最小供电电压 (Vsup)	1.7 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN SILVER COPPER
端子形式	BALL
端子节距	0.75 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	6 mm
Base Number Matches	1

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4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory

Features

Async/Page/Burst

CellularRAM

1.0 Memory

MT45W256KW16BEGB

Features

• Single device supports asynchronous, page, and

burst operations

• Random access time: 70ns

• V

, V

Q voltages

–

1.7–1.95V V

–

1.7–3.6V

• Page mode read access

–

16-word page size

–

Interpage read access: 70ns

–

Intrapage read access: 20ns

• Burst mode write access: continuous burst

• Burst mode read access

–

4, 8, or 16 words or continuous burst

–

MAX clock rate: 104 MHz (

CLK = 9.62ns)

–

Burst initial latency: 38.5ns (4 clocks) at 104 MHz

–

ACLK: 7ns at 104 MHz

• Low power consumption

–

Asynchronous read: <20mA

–

Intrapage read: <15mA

–

Intrapage read initial access, burst read:

(38.5ns [4 clocks] at 104 MHz) <35mA

–

Continuous burst read: <28mA

–

Standby: <60µA

–

Deep power-down (DPD): <10µA (TYP at 25°C)

• Low-power features

–

Partial-array refresh (PAR)

–

DPD mode

Figure 1:

54-Ball VFBGA Ball Assignment

LB#

OE#

CRE

DQ8

UB#

CE#

DQ0

DQ9

DQ10

DQ1

DQ2

DQ11

A17

DQ3

DQ12

A16

DQ4

DQ14

DQ13

A14

A15

DQ5

DQ6

DQ15

A12

A13

WE#

DQ7

DNU

A10

A11

WAIT

CLK

ADV#

Top view

(Ball down)

Options

• Configuration

–

256K x 16

• Package

–

54-ball VFBGA (“green”)

• Access time

–

70ns

• Frequency

–

80 MHz

–

104 MHz

• Standby power

–

Standard

Designator

MT45W256KW16BE

-70

None

Options (continued)

• Operating temperature range

–

Wireless (–30°C to +85°C)

–

Industrial (–40°C to +85°C)

Designator

Notes: 1. The 3.6V I/O and the –30°C wireless temper-

ature exceed the CellularRAM Workgroup 1.0

specification.

2. Contact factory for availability.

Part Number Example:

MT45W256KW16BEGB-701WT

PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5

8mb_4mb_burst_cr1_0_p22z__1.fm - Rev. B 4/ 08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Output Impedance (BCR[5]) Default = Outputs Use Full-Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .26

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5

4mb_burst_cr1_0_p22zTOC.fm - Rev. B 4/ 08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Figures

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Figure 39:

Figure 40:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

Figure 45:

Figure 46:

Figure 47:

Figure 48:

Figure 49:

54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Functional Block Diagram (256K x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Asynchronous Mode Configuration Register Write Followed by READ ARRAY Operation . . . . . . .18

Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . . .19

Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . .20

Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . . .21

Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Latency Counter (Variable Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Four-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . . .43

CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Output Delay in Continuous Burst Write with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . . . .49

Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Asynchronous WRITE Followed by Burst READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .55

Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5

4mb_burst_cr1_0_p22zLOF.fm - Rev. B 4/ 08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Tables

Table 1:

Table 2:

Table 3:

Table 4:

Table 5:

Table 6:

Table 7:

Table 8:

Table 9:

Table 10:

Table 11:

Table 12:

Table 13:

Table 14:

VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus Operations: Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations: Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5

4mb_burst_cr1_0_p22zLOT.fm - Rev. B 4/ 08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory

General Description

Micron

CellularRAM

is a high-speed, CMOS PSRAM memory developed for low-

power, portable applications. The MT45W256KW16BEGB is a 4Mb DRAM core

device organized as 256K x 16 bits. This device includes an industry-standard burst

mode Flash interface that dramatically increases read/write bandwidth compared with

other low-power SRAM or pseudo-SRAM (PSRAM) offerings.

For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-

parent self refresh mechanism. The hidden refresh requires no additional support from

the system memory controller and has no significant impact on device read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM

array. These registers are automatically loaded with default settings during power-up

and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh.

This CellularRAM product includes two system-accessible mechanisms to minimize

standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM

array that contains essential data. Deep power-down (DPD) halts the REFRESH opera-

tion altogether and is used when no vital information is stored in the device. These two

refresh mechanisms are accessed through the RCR.

Functional Block Diagrams

Figure 2:

Functional Block Diagram (256K x 16)

A[17:0]

Address decode

logic

256K x 16

DRAM

memory

array

Input/

output

MUX

and

buffers

DQ[7:0]

DQ[15:8]

Refresh configuration

Bus configuration

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

Control

logic

Note:

Functional block diagrams illustrate simplified device operation. See the ball description

table and timing diagrams for detailed information.

PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5

8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT45W256KW16BEGB-708IT相似产品对比

	MT45W256KW16BEGB-708IT	MT45W256KW16BEGB-708 WT TR	MT45W256KW16BEGB-701IT	MT45W256KW16BEGB-701WT
描述	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 1 MM HEIGHT 0.75 MM PITCH, GREEN, VFBGA-54	IC PSRAM 4M PARALLEL 54VFBGA	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 1 MM HEIGHT 0.75 MM PITCH, GREEN, VFBGA-54	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 1 MM HEIGHT 0.75 MM PITCH, GREEN, VFBGA-54
技术	CMOS	PSRAM（伪 SRAM）	CMOS	CMOS
是否Rohs认证	符合	-	符合	符合
零件包装代码	BGA	-	BGA	BGA
包装说明	VFBGA, BGA54,6X9,30	-	VFBGA, BGA54,6X9,30	VFBGA, BGA54,6X9,30
针数	54	-	54	54
Reach Compliance Code	compliant	-	unknown	compliant
ECCN代码	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A
最长访问时间	70 ns	-	70 ns	70 ns
I/O 类型	COMMON	-	COMMON	COMMON
JESD-30 代码	R-PBGA-B54	-	R-PBGA-B54	R-PBGA-B54
JESD-609代码	e1	-	e1	e1
长度	8 mm	-	8 mm	8 mm
内存密度	4194304 bit	-	4194304 bit	4194304 bit
内存集成电路类型	PSEUDO STATIC RAM	-	PSEUDO STATIC RAM	PSEUDO STATIC RAM
内存宽度	16	-	16	16
功能数量	1	-	1	1
端子数量	54	-	54	54
字数	262144 words	-	262144 words	262144 words
字数代码	256000	-	256000	256000
工作模式	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	85 °C	-	85 °C	85 °C
最低工作温度	-40 °C	-	-40 °C	-40 °C
组织	256KX16	-	256KX16	256KX16
输出特性	3-STATE	-	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	VFBGA	-	VFBGA	VFBGA
封装等效代码	BGA54,6X9,30	-	BGA54,6X9,30	BGA54,6X9,30
封装形状	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	-	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL	-	PARALLEL	PARALLEL
电源	1.8,1.8/3.3 V	-	1.8,1.8/3.3 V	1.8,1.8/3.3 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified
座面最大高度	1 mm	-	1 mm	1 mm
最大待机电流	0.00001 A	-	0.00001 A	0.00001 A
最大压摆率	0.035 mA	-	0.035 mA	0.035 mA
最大供电电压 (Vsup)	1.95 V	-	1.95 V	1.95 V
最小供电电压 (Vsup)	1.7 V	-	1.7 V	1.7 V
表面贴装	YES	-	YES	YES
温度等级	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
端子面层	TIN SILVER COPPER	-	TIN SILVER COPPER	TIN SILVER COPPER
端子形式	BALL	-	BALL	BALL
端子节距	0.75 mm	-	0.75 mm	0.75 mm
端子位置	BOTTOM	-	BOTTOM	BOTTOM
宽度	6 mm	-	6 mm	6 mm

MT45W256KW16BEGB-708IT

MT45W256KW16BEGB-708IT概述

MT45W256KW16BEGB-708IT规格参数

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MT45W256KW16BEGB-708IT相似产品对比

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