product family. Designed to fit in a small 6-pin DFN
or 6-pin SOT package for high performance
applications, the PL611s-26 offers very low phase
noise, jitter, and power consumption, while offering
up to 2 clock outputs.. The Frequency Switching
(FSEL) capability of PL611s-26 allows for
programming two sets of frequencies, while the
power down feature of PL611s-26, when activated,
allows the IC to consume less than 10 A of power.
PL611s-26’s programming flexibility allows
generating any output using Reference input signal.
BLOCK DIAGRAM
FIN
F
REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
P-Counter
(5-bit)
F
OUT
= F
VCO
/ (2 * P)
Programmable Function
CLK0
FSEL
Programming
Logic
OE, PDB,
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 1
(Preliminary)
PL611s-26
1.8V-3.3V PicoPLL
TM
Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
PDB - input
•
CLK1 – output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
OE, PDB, CLK1
FIN
OE,PDB,CLK1
GND
1
2
3
6
5
4
FSEL
VDD
CLK0
GND
FIN
1
2
3
6
5
4
CLK0
VDD
FSEL
PL611s-26
PL611s-26
PL611s-26
PL611s-26
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm)
mm
PIN DESCRIPTION
Name
Pin Assignment
DFN Pin# SOT Pin #
Type
Description
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60K pull up resistor (OE and PDB functions only).
2
1
I/O
Pin State
0
1 (default)
GND
FIN
3
1
2
3
P
I
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
OE,
PDB,
CLK1
FSEL
6
4
I
GND connection
Reference input pin
Frequency Switching Input pin. This pin has an internal 60K
resistor.
FSEL
State
0
1 (default)
Frequency 2
Frequency 1
pull up
VDD
CLK0
5
4
5
6
P
O
VDD connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
(Preliminary)
PL611s-26
1.8V-3.3V PicoPLL
TM
Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-26 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-26 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 200MHz. This flexible design allows the PL611s-26 to deliver any PLL
generated frequency, F
REF
(Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-26 are mentioned below:
PLL Programming
The PLL in the PL611s-26 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-26 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/CLK1 pin description below). The output of
CLK0 can be configured as the PLL output
(F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output, or
F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is determined by the power supply voltage
as shown below:
Clock Output (CLK1)
The CLK1 feature allows the PL611s-26 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference (Ref Clk ) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-26 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull
up resistor giving a default condition of logic “1”.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-26 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10 A of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 3
(Preliminary)
PL611s-26
1.8V-3.3V PicoPLL
TM
Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
1
0.9
0.1
CONDITIONS
MIN.
TYP.
MAX.
200
166
133
V
DD
V
DD
200
166
133
2
10
UNITS
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
PDB Function; Ta=25º C, 15pF Load
Output Rise Time
15pF Load, 10/90% V
DD
, High Drive, 3.3V
Output Fall Time
15pF Load, 90/10% V
DD
, High Drive, 3.3V
Duty Cycle
V
DD
/2
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
45
1.2
1.2
50
70
2
1.7
1.7
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 4
(Preliminary)
PL611s-26
1.8V-3.3V PicoPLL
TM
Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Stand By Current, with Loaded
Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
CONDITIONS
@ V
DD
=3.3V, 27MHz,
load=15pF
@ V
DD
=2.5V, 27MHz,
load=15pF
@ V
DD
=1.8V, 27MHz,
load=15pF
When PDB=0
MIN.
TYP.
5.5
3.8
1.8*
MAX.
UNITS
mA
mA
mA
<10
1.62
3.63
0.4
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
16
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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