THC63LVD1022_Rev.1.02_E
THC63LVD1022
30Bit Color/150Mpps Dual-Link LVDS to LVCMOS converter
General Description
The THC63LVD1022 LVDS (Low Voltage Differential
Signaling) converter is designed to support pixel data
transmission between Host and Flat Panel Display up to
Full-HD 1080p resolutions.
The THC63LVD1022 receives dual channel LVDS data stream
and transmits LVTTL/LVCMOS data through Dual Pixel Link
Input / Single Link output conversion.
At a transmit data of 150Mpixel/sec, 30bits/pixel and 5bits of
timing and control data (HSYNC, VSYNC, DE) are received at
an effective rate of 525Mbps per LVDS channel.
Features
½20MHz
to 75MHz 30bits/pixel dual-Link LVDS input
½Up
to 150MHz 30bit s/pixel single port LVCMOS output
½Operating
Temperature Range : 0 to 85
°C
½LVDS
input skew margin: ±400ps at 75MHz
½Dual
input / Single output mode [clkout = 2x clkin]
½Output
Enable / Disable mode supported
½No
Special Start-up Sequence Required
½100pin
TQFP Package
½3.3V
single voltage power supply.
½PLL
requires no external components.
½Environmental
laws and regulations compliance
(ex. EU RoHS)
Application
½Security
Camera / Industrial Camera
½Medium
and Small Size Panel
½Tablet
PC / Notebook PC
½Multi
Function Printer
½Industrial
Equipment
½Medical
Equipment Monitor
Block Diagram
Figure 1. Block Diagram
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THine Electronics, Inc.
THC63LVD1022_Rev.1.02_E
Pin Description
Pin Name
RA1+, RA1-
RB1+, RB1-
RC1+, RC1-
RD1+, RD1-
RE1+, RE1-
RCLK1+,RCLK1-
RA2+, RA2-
RB2+, RB2-
RC2+, RC2-
RD2+, RD2-
RE2+, RE2-
RCLK2+,RCLK2-
TEST, TEST2
Pin #
2, 1
4, 3
6, 5
10, 9
12, 11
8, 7
15, 14
17, 16
19, 18
23, 22
25, 24
21, 20
72, 43
Direction
Type
Description
LVDS 1st Link Data In.
LVDS
LVDS Clock Input for 1st Link.
LVDS 2nd Link Data In.
OE
29
Input
MLSB
71
MAP2 ~ 0
62, 55, 30
LVTTL
LVDS Clock Input for 2nd Link.
Reserved
L: Normal Operation
(Table. 10)
Output Enable
H: Normal Operation
L: Fix Output signals(Hold the previous logic value)
Output bit order selection
H: MSB = 9 / LSB = 0
L: MSB = 0 / LSB = 9
Output color mapping selection
MAP0:1:2
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
Rch
R
R
B
B
G
G
R
R
RGB
Gch
G
B
R
G
R
B
G
G
Bch
B
G
G
R
B
R
B
B
Table 1. Pin Description
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THine Electronics, Inc.
THC63LVD1022_Rev.1.02_E
Pin Description (Continued)
Pin Name
DE
VSYNC
HSYNC
R9 ~ 0
G9 ~ 0
B9 ~ 0
CLKOUT
VCC
Pin #
97
96
95
48, 47, 46, 42, 41,
40, 36, 35, 34, 33
67, 66, 65, 61, 60,
59, 54, 53, 52, 51
92, 91, 90, 86, 85,
84, 81, 80, 79, 78
75
26, 31, 37, 44, 49,
56, 63, 70, 74, 77,
83, 89, 94, 100
13, 27, 32, 38, 45,
50, 57, 64, 69, 73,
76, 82, 88, 93, 99
28, 39, 58, 68, 87,
98
Direction
Type
Data Enable Output
Vsync Output
Hsync Output
Pixel Data Output(Rch)
Output
LVCMOS
Pixel Data Output(Gch)
Pixel Data Output(Bch)
Clock Output
Power Supply Pins
-
Description
GND
Ground Pins
CAP
Decoupling cap.
External 0.1uF or more capacitance required.
Table 2. Pin Description
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THine Electronics, Inc.
THC63LVD1022_Rev.1.02_E
Absolute Maximum Ratings
Parameter
Supply Voltage (VCC)
LVCMOS/TTL Input Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Min
-0.3
-0.3
-0.3
-
-55
Max
+4.0
VCC + 0.3
VCC + 0.3
+125
+125
Unit
V
V
V
°C
°C
Table 3. Absolute Maximum Rating
Recommended Operating Conditions
Symbol
-
Ta
-
Parameter
Min
Typ
All Supply Voltage
3.0
3.3
Operating Ambient Temperature
0
25
LVDS Input
20
-
Clock Frequency
LVCMOS Output
40
-
Table 4. Recommended Operating Conditions
Max
3.6
+85
75
150
Unit
V
°C
MHz
“Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
“Absolute Maximum Rating” values also include behavior of overshooting and undershooting.
Equivalent LVDS Input Schematic Diagram
Figure 3. LVDS Input Schematic Diagram
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THine Electronics, Inc.
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