ADVANCE INFORMATION
PE9704
Product Description
Peregrine’s PE9704 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLLs.
The PE9704 features a ÷10/11 dual modulus prescaler,
counters, a phase comparator, and a charge pump, as
shown in Figure 1. Counter values are programmable
through a serial interface, and can also be directly hard
wired.
The PE9704 is optimized for commercial space
applications. Single Event Latch-up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10
-9
errors per bit / day. Fabricated in Peregrine’s
patented UTSi® (Ultra Thin Silicon) CMOS technology,
the PE9704 offers excellent RF performance and intrinsic
radiation tolerance.
3.0 GHz Integer-N PLL for Rad
Hard Applications
Features
•
3.0 GHz operation
•
÷10/11 dual modulus prescaler
•
Selectable for either charge
pump or phase detector outputs
•
Serial interface or hardwired
programmable
•
Ultra-low phase noise
•
SEU < 10
-9
errors / bit-day
•
100 Krad (Si) total dose
•
44-lead CQFJ
Figure 1. Block Diagram
Prescaler
10 / 11
MSEL
F
IN
Main
Counter
13
Charge
Pump
CP
Serial
Control
3
20-Bit
Frequency
Register
f
p
20
19*
f
c
Phase
Detector
PD_U
PD_D
M(8:0)
Direct
A(3:0)
Control
R(5:0)
F
R
LD
6
6
C ext
R Counter
* prescaler bypass not available in Direct mode
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 1 of 13
PE9704
Advance Information
Figure 2. Pin Configuration
GND
GND
GND
ENH
V
DD
LD
R
3
R
2
R
1
R
0
F
R
6
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
F_WR, M
4
DATA, M
5
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
C
EXT
V
DD
PD_U
PD_D
GND
CP
V
DD
D
OUT
V
DD
CP
SEL
GND
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
CLOCK, M
6
D
MODE
M
7
M
8
A
0
E_WR, A
1
A
2
A
3
V
DD
F
IN
GND
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
F_WR
M
4
DATA
M
5
Interface Mode
Both
Direct
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
Serial
Direct
Serial
Direct
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on F_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-bit
frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
M Counter bit5
File No. 70/0083~00A
15
16
Copyright
Peregrine Semiconductor Corp. 2001
| |
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 13
PE9704
Advance Information
Pin No.
17
Pin Name
GND
CLOCK
M
6
Interface Mode
Both
Serial
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
Direct
Both
Both
Both
Both
Both
Serial
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Type
Ground
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Description
18
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR “low”)
or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK.
M Counter bit6
M Counter bit7
M Counter bit8 (MSB)
A Counter bit0
Selects direct interface mode (D
MODE
=1) or serial interface mode (D
MODE
=0)
Same as pin 1
A Counter bit1
A Counter bit2
A Counter bit3 (MSB)
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
Ground.
Ground.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Note 2:
M
7
M
8
A
0
D
MODE
V
DD
A
1
A
2
A
3
F
IN
GND
GND
CP
SEL
V
DD
D
OUT
V
DD
CP
V
DD
PD_D
PD_U
V
DD
C
EXT
GND
GND
F
R
ENH
LD
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Charge pump select input. Selects whether the charge pump output is enabled
(CP
SEL
=1), or the PD_U / PD_D outputs are enabled (CP
SEL
=0).
Same as pin 1
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to D
OUT
through enhancement register programming.
Same as pin 1
Charge Pump output. Charge pump current is sourced for “up” when f
c
leads f
p
and
sinked for “down” when f
c
lags f
p
. Active only when CP
SEL
=1.
Same as pin 1
PD_D pulses down when f
p
leads f
c
. Active only when CP
SEL
=0
PD_U pulses down when f
c
leads f
p
. Active only when CP
SEL
=0
(Note 1)
Output
Same as pin 1
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series resistor.
Connecting C
EXT
to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
Ground
Ground
Input
Output,
OD
Input
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Lock detect output, the open-drain logical inversion of C
EXT
. When the loop is locked,
LD is high impedance; otherwise LD is a logic low (“0”).
V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 3 of 13
PE9704
Advance Information
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Electrostatic Discharge (ESD) Precautions
Units
V
V
mA
mA
°C
4.0
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
V
DD
+ 0.3
+10
+10
150
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD voltage (Human Body
Model) – Note 1
Level
1000
Units
V
Note 1:
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Copyright
Peregrine Semiconductor Corp. 2001
File No. 70/0083~00A
| |
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 13
PE9704
Advance Information
Table 5. DC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
High level input voltage
Low level input voltage
High level input current
Low level input current
High level input current
Low level input current
Output voltage LOW
Output voltage HIGH
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
10
24
Max
Units
mA
mA
V
31
Digital Inputs: All except F
R
, F
IN
(all digital inputs have 70k ohm pull-up resistors)
V
IH
V
IL
I
IH
I
IL
I
IHR
I
ILR
V
OLD
V
OHD
V
OLC
V
OHC
V
OLLD
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
I
out
= 6 mA
I
out
= -3 mA
I
out
= 100 mA
I
out
= -100 mA
I
out
= 6 mA
V
DD
- 0.4
0.4
V
DD
- 0.4
0.4
-100
0.4
-1
+100
0.7 x V
DD
0.3 x V
DD
+70
V
µA
µA
µA
µA
V
V
V
V
V
Reference Divider input: F
R
Counter and phase detector outputs: f
c
, f
p
.
Lock detect outputs: C
EXT
, LD
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 5 of 13
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
