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74HC373DB,118

产品描述Latch Transparent 3-ST 8-CH D-Type 20-Pin SSOP T/R
产品类别锁存器   
文件大小275KB,共17页
制造商Nexperia
官网地址https://www.nexperia.com
标准
下载文档 详细参数 选型对比 全文预览

74HC373DB,118概述

Latch Transparent 3-ST 8-CH D-Type 20-Pin SSOP T/R

74HC373DB,118规格参数

参数名称属性值
欧盟限制某些有害物质的使用Compliant
ECCN (US)EAR99
Part StatusLTB
HTS8542.39.00.01
类型
Type
D-Type
Logic FamilyHC
Latch ModeTransparent
Number of Channels per Chip8
Number of Elements per Chip1
Number of Inputs per Chip8
Number of Input Enables per Element1
Number of Selection Inputs per Element0
Number of Outputs per Chip8
Number of Output Enables per Element1
Bus HoldNo
Set/ResetNo
PolarityNon-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)150@2V|30@4.5V|26@6V
Absolute Propagation Delay Time (ns)265
Process TechnologyCMOS
输出类型
Output Type
3-State
Maximum Low Level Output Current (mA)7.8
Maximum High Level Output Current (mA)-7.8
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)5
Maximum Operating Supply Voltage (V)6
Maximum Quiescent Current (uA)8
Propagation Delay Test Condition (pF)50
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
系列
Packaging
Tape and Reel
Supplier PackageSSOP
Pin Count20
MountingSurface Mount
Package Height1.8(Max)
Package Length7.4(Max)
Package Width5.4(Max)
PCB changed20

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74HC373; 74HCT373
Rev. 7 — 22 July 2020
Octal D-type transparent latch; 3-state
Product data sheet
1. General description
The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs
enter the latches. In this condition the latches are transparent, a latch output will change each time
its corresponding D-input changes. When LE is LOW the latches store the information that was
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
Input levels:
For 74HC373: CMOS level
For 74HCT373: TTL level
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC373DB,118相似产品对比

74HC373DB,118 74HC373PW,112 74HC373D,653 74HC373PW,118
描述 Latch Transparent 3-ST 8-CH D-Type 20-Pin SSOP T/R Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP Bulk Latch Transparent 3-ST 8-CH D-Type 20-Pin SO T/R Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R
欧盟限制某些有害物质的使用 Compliant Compliant Compliant Compliant
ECCN (US) EAR99 EAR99 EAR99 EAR99
Part Status LTB LTB Active Active
HTS 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01
类型
Type
D-Type D-Type D-Type D-Type
Logic Family HC HC HC HC
Latch Mode Transparent Transparent Transparent Transparent
Number of Channels per Chip 8 8 8 8
Number of Elements per Chip 1 1 1 1
Number of Inputs per Chip 8 8 8 8
Number of Input Enables per Element 1 1 1 1
Number of Outputs per Chip 8 8 8 8
Number of Output Enables per Element 1 1 1 1
Bus Hold No No No No
Set/Reset No No No No
Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns) 150@2V|30@4.5V|26@6V 30@4.5V|26@6V|150@2V 150@2V|30@4.5V|26@6V 150@2V|30@4.5V|26@6V
Absolute Propagation Delay Time (ns) 265 265 265 265
Process Technology CMOS CMOS CMOS CMOS
输出类型
Output Type
3-State 3-State 3-State 3-State
Maximum Low Level Output Current (mA) 7.8 7.8 7.8 7.8
Maximum High Level Output Current (mA) -7.8 -7.8 -7.8 -7.8
Minimum Operating Supply Voltage (V) 2 2 2 2
Typical Operating Supply Voltage (V) 5 5 5 5
Maximum Operating Supply Voltage (V) 6 6 6 6
Maximum Quiescent Current (uA) 8 8 8 8
Propagation Delay Test Condition (pF) 50 50 50 50
Minimum Operating Temperature (°C) -40 -40 -40 -40
Maximum Operating Temperature (°C) 125 125 125 125
系列
Packaging
Tape and Reel Bulk Tape and Reel Tape and Reel
Supplier Package SSOP TSSOP SO TSSOP
Pin Count 20 20 20 20
Mounting Surface Mount Surface Mount Surface Mount Surface Mount
Package Height 1.8(Max) 0.95(Max) 2.45(Max) 0.95(Max)
Package Length 7.4(Max) 6.6(Max) 13(Max) 6.6(Max)
Package Width 5.4(Max) 4.5(Max) 7.6(Max) 4.5(Max)
PCB changed 20 20 20 20

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