Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R
| 参数名称 | 属性值 |
| 欧盟限制某些有害物质的使用 | Compliant |
| ECCN (US) | EAR99 |
| Part Status | Active |
| HTS | 8542.39.00.01 |
| 类型 Type | D-Type |
| Logic Family | HC |
| Latch Mode | Transparent |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Number of Inputs per Chip | 8 |
| Number of Input Enables per Element | 1 |
| Number of Selection Inputs per Element | 0 |
| Number of Outputs per Chip | 8 |
| Number of Output Enables per Element | 1 |
| Bus Hold | No |
| Set/Reset | No |
| Polarity | Non-Inverting |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 150@2V|30@4.5V|26@6V |
| Absolute Propagation Delay Time (ns) | 265 |
| Process Technology | CMOS |
| 输出类型 Output Type | 3-State |
| Maximum Low Level Output Current (mA) | 7.8 |
| Maximum High Level Output Current (mA) | -7.8 |
| Minimum Operating Supply Voltage (V) | 2 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Operating Supply Voltage (V) | 6 |
| Maximum Quiescent Current (uA) | 8 |
| Propagation Delay Test Condition (pF) | 50 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 125 |
| 系列 Packaging | Tape and Reel |
| Supplier Package | TSSOP |
| Pin Count | 20 |
| Mounting | Surface Mount |
| Package Height | 0.95(Max) |
| Package Length | 6.6(Max) |
| Package Width | 4.5(Max) |
| PCB changed | 20 |
| 74HC373PW,118 | 74HC373DB,118 | 74HC373PW,112 | 74HC373D,653 | |
|---|---|---|---|---|
| 描述 | Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R | Latch Transparent 3-ST 8-CH D-Type 20-Pin SSOP T/R | Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP Bulk | Latch Transparent 3-ST 8-CH D-Type 20-Pin SO T/R |
| 欧盟限制某些有害物质的使用 | Compliant | Compliant | Compliant | Compliant |
| ECCN (US) | EAR99 | EAR99 | EAR99 | EAR99 |
| Part Status | Active | LTB | LTB | Active |
| HTS | 8542.39.00.01 | 8542.39.00.01 | 8542.39.00.01 | 8542.39.00.01 |
| 类型 Type |
D-Type | D-Type | D-Type | D-Type |
| Logic Family | HC | HC | HC | HC |
| Latch Mode | Transparent | Transparent | Transparent | Transparent |
| Number of Channels per Chip | 8 | 8 | 8 | 8 |
| Number of Elements per Chip | 1 | 1 | 1 | 1 |
| Number of Inputs per Chip | 8 | 8 | 8 | 8 |
| Number of Input Enables per Element | 1 | 1 | 1 | 1 |
| Number of Outputs per Chip | 8 | 8 | 8 | 8 |
| Number of Output Enables per Element | 1 | 1 | 1 | 1 |
| Bus Hold | No | No | No | No |
| Set/Reset | No | No | No | No |
| Polarity | Non-Inverting | Non-Inverting | Non-Inverting | Non-Inverting |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 150@2V|30@4.5V|26@6V | 150@2V|30@4.5V|26@6V | 30@4.5V|26@6V|150@2V | 150@2V|30@4.5V|26@6V |
| Absolute Propagation Delay Time (ns) | 265 | 265 | 265 | 265 |
| Process Technology | CMOS | CMOS | CMOS | CMOS |
| 输出类型 Output Type |
3-State | 3-State | 3-State | 3-State |
| Maximum Low Level Output Current (mA) | 7.8 | 7.8 | 7.8 | 7.8 |
| Maximum High Level Output Current (mA) | -7.8 | -7.8 | -7.8 | -7.8 |
| Minimum Operating Supply Voltage (V) | 2 | 2 | 2 | 2 |
| Typical Operating Supply Voltage (V) | 5 | 5 | 5 | 5 |
| Maximum Operating Supply Voltage (V) | 6 | 6 | 6 | 6 |
| Maximum Quiescent Current (uA) | 8 | 8 | 8 | 8 |
| Propagation Delay Test Condition (pF) | 50 | 50 | 50 | 50 |
| Minimum Operating Temperature (°C) | -40 | -40 | -40 | -40 |
| Maximum Operating Temperature (°C) | 125 | 125 | 125 | 125 |
| 系列 Packaging |
Tape and Reel | Tape and Reel | Bulk | Tape and Reel |
| Supplier Package | TSSOP | SSOP | TSSOP | SO |
| Pin Count | 20 | 20 | 20 | 20 |
| Mounting | Surface Mount | Surface Mount | Surface Mount | Surface Mount |
| Package Height | 0.95(Max) | 1.8(Max) | 0.95(Max) | 2.45(Max) |
| Package Length | 6.6(Max) | 7.4(Max) | 6.6(Max) | 13(Max) |
| Package Width | 4.5(Max) | 5.4(Max) | 4.5(Max) | 7.6(Max) |
| PCB changed | 20 | 20 | 20 | 20 |
嵌入式系统
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DSP 与 ARM 处理器
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