SAF784x
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
Product data sheet
1. General description
The SAF784x is a single-chip solution CD audio decoder with on-chip MP3 and WMA
decoding, digital servo, audio DAC, sample-rate converter, preamplifier, laser driver and
integrated ARM7TDMI-S microprocessor. The device contains all of the required ROM
and RAM, including an internal re-programmable Flash ROM, and is targeted at low-cost
compressed audio CD applications. The design is a one-chip CD audio decoder IC, with
additions to allow low-cost system implementation of MP3 and WMA decoding.
2. Features
2.1 Features
I
Channel decoder and digital servo
I
32-bit embedded ARM7 RISC microprocessor supporting both 32-bit and 16-bit
(‘Thumb’) instruction sets
I
Maximum ARM operating frequency of 76 MHz, equivalent to 68 MIPS
I
Decoding of compressed audio stream (MP3/WMA) on ARM7 core
I
All memories required for MP3/WMA decoding embedded on chip: combination of
130 kB mask-programmed internal program ROM (to reduce wait-states on
high-speed code, e.g. decompression algorithms), 42 kB boot ROM, 64 kB of internal
re-programmable Flash ROM (for simple re-programming of application code) 110 kB
internal SRAM
I
Programmable clock frequency for ARM microprocessor - allowing users to trade-off
power consumption and processing power depending on requirements
I
Block decoder hardware to perform C3 error correction
I
Sample-rate converter circuit to convert compressed audio sample rates (in the range
8 kHz to 48 kHz) to an output rate of 44.1 kHz
I
Microprocessor access to digital representations of the diode input signals from the
optical pickup; the microprocessor can also generate the servo output signals RA, FO,
SL, allowing the possibility of additional servo algorithms in software
I
Programmable PDM outputs (effectively sine and cosine) to allow use of stepper motor
for sledge mechanism
I
Microprocessor access to audio streams, both from the internal CD decoder and an
external stereo auxiliary input (e.g. an analog source from a tuner, converted to digital
via on-chip ADCs) to allow audio processing algorithms in the ARM microprocessor,
e.g. bass boost, volume control
I
Four general-purpose analog inputs (A_IN1 to A_IN4) allowing the ARM
microprocessor access to other external analog signals, e.g. low-cost keypad,
temperature sensor, via on-chip ADCs
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
I
Two additional analog audio inputs (AUX_L, AUX_R) to allow the ARM microprocessor
access to external audio signals (e.g. tuner); allows audio algorithms (e.g. bass boost)
to be performed on external audio signals
I
Real-time clock operated from separate 32 kHz crystal; allows low-power Standby
mode with real-time clock still operational
I
Watchdog timer
I
I
2
S-bus, S/PDIF, subcode (V4) and subcode sync outputs
I
32 GPIOs
I
Two standard UART channels
I
Two external interrupt pins
I
I
2
C-bus interface configurable for master or slave modes, supporting 100 kbit/s and
400 kbit/s standards
I
Slave I
2
S-bus mode, in which the channel decoder can synchronize the CD playback
speed to an I
2
S-bus clock input
I
Integrated digital HF/Mirror detector with measurement of minimum and maximum
peak values, amplitude and offset
I
Integrated CD-text decoder
I
Up to 6× decode speed, CLV or CAV modes
I
LQFP144 package with 0.5 mm pin pitch
I
Separate left and right channel digital silence detection available on KILL pins
I
Digital silence detection available on loopback data from external source as well as
internal data
I
‘Filterless’ pseudo bit stream audio DAC with minimal external components
I
Stereo line outputs for audio DAC
I
Loopback mode allowing the use of integrated DAC with external I
2
S-bus/EIAJ sources
I
Compatible with voltage mode mechanisms
I
On-chip buffering and filtering of the diode signals from the mechanism in order to
optimize the signals for the decoder and servo parts
I
LF (servo) signals converted to digital representations by Sigma-Delta ADCs shared
between pairs of channels to minimize DC offset between channels
I
HF part summed from signals D1 to D4 and converted to digital signals by HF 6-bit
ADC
I
Selectable DC offset cancellation of quiescent mechanism voltages and dark currents,
digitally controlled; additional fine DC-offset cancellation in digital domain
I
Eye pattern monitor system to observe selectable points within the analog pre-amp
I
Current and average jitter values available via registers
I
On-chip laser power control, up to maximum currents of 120 mA
I
Laser on-off control, including ‘soft’-start control - zero-to-nominal output power in
1 ms
I
Monitor control and feedback circuit to maintain nominal output power throughout laser
life
I
Configured for Nsub (N-substrate) monitor diode
I
JTAG interface for device access and ARM code development (compatible with ARM
multi-ICE)
I
All digital input pins 5 V tolerant
I
Low-latency static memory interface to access a maximum of two 2 MB memory
SAF784X_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
2 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
I
This product has been qualified in accordance with AEC-Q100
2.2 Formats
Reads the following CD-decode formats
I
CD-R
I
CD-RW
I
CD-DA (CD
Red Book; IEC 60908)
I
CD-ROM (Mode 1 and Mode 2)
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CD-MP3
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CD-WMA
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Video CD
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SACD (CD layer only)
I
Support 80 minute to 100 minute CD playback
I
Multi-session discs
3. Ordering information
Table 1.
Ordering information
Package
Name
SAF7846HL
SAF7847HL
LQFP144
Description
plastic low profile quad flat package; 144 leads; body 20
×
20
×
1.4 mm
Version
SOT486-1
Type number
SAF784X_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
3 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
4. Block diagram
CHANNEL DECODER
HF ADC
PARALLEL
DATA
INTERFACE
BLOCK DECODER
SEGMENTATION
MANAGER
BLOCK
BUFFER
MEMORY
AHB
INTERFACE
DIGITAL
DECODER
PARALLEL INPUT AND
OUTPUT INTERFACES
MOTOR
CONTROL
I
2
S-BUS
OUTPUT
C3 ERCO
REGISTER
INTERFACE
EBU
INTERFACE
LF ANALOG ADCs
AHB
ADDRESS
DECODER
AHB
INTERFACE
AHB
INTERFACE
DMA
CONTROLLER
CHANNEL
CLOCK
CONTROL
REGISTER
INTERFACE
PROGRAMMABLE
ROM (130 kB)
ARM7 CPU
SERVO
GENERAL PURPOSE ADCs
FLEXI
SERVO
INTERFACE
SLEDGE
STEPPER
MOTOR
DRIVER
BOOT ROM (42 kB)
AHB-to-VPB
FLASH (64 kB)
DIGITAL
SERVO
TIMER (× 2)
SMIU
UART (× 2)
GENERAL
PURPOSE
ADC
PROCESSOR
REGISTER
INTERFACE
AHB INTERFACE
WATCHDOG
TIMER
AHB REGISTERS
I
2
C-BUS
RAM (110 kB)
GPIO
REAL-TIME
CLOCK
CLOCK
ANALOG
PLL
ANALOG
LASER
DRIVER
AUDIO
DAC LINE
OUTPUTS
INTERRUPT
CONTROLLER
AUDIO PROCESSOR
EBU
BUFFER
SRC
CLOCK CONTROL
VPB SUB-SYSTEM
MULTI-LAYER AHB SUB-SYSTEM
001aag353
Fig 1.
SAF784x top level block diagram
SAF784X_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
4 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
5. Pinning information
5.1 Pinning
144
109
108
1
SAF784x
36
37
72
73
001aag352
Fig 2.
SAF784x pinning diagram
5.2 Pin description
Table 2.
Pin description
All digital inputs and bidirectional pins are 5 V tolerant.
Symbol
SL_SIN
COS/GPIO31
LPOWER
LASER
MONITOR
VSSA1
HF_MON
VDDA1
D1
D2
D3
D4
R1
R2
AUX_L
AUX_R
VDDA2
OPU_REF_OUT
VSSA2
OSCOUT
OSCIN
VDDA3
SAF784X_2
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Type
[1]
Description
O
B
P
P
AI
P
AIO
P
AI
AI
AI
AI
AI
AI
AI
AI
P
AO
P
AO
AI
P
sledge actuator/stepper motor PDM output (sine)
stepper motor PDM output (cosine)/general purpose I/O 31
laser power supply
laser diode drive
laser monitor diode input
analog ground 1
HF monitor output signal
analog supply voltage 1
central diode signal voltage input
central diode signal voltage input
central diode signal voltage input
central diode signal voltage input
satellite diode signal voltage input
satellite diode signal voltage input
auxiliary audio left signal input
auxiliary audio right signal input
analog supply voltage 2
OPU reference voltage
analog ground 2
crystal or resonator output
crystal or resonator input
analog supply voltage 3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
5 of 93
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