NVT2008; NVT2010
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 3 — 27 January 2014
Product data sheet
1. General description
The NVT2008/NVT2010 are bidirectional voltage level translators operational from 1.0 V
to 3.6 V (V
ref(A)
) and 1.8 V to 5.5 V (V
ref(B)
), which allow bidirectional voltage translations
between 1.0 V and 5 V without the need for a direction pin in open-drain or push-pull
applications. Bit widths of 8-bit to 10-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197
.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (R
on
) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by V
ref(B)
. To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.2 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.8 V V
ref(A)
and 3.3 V or 5 V V
ref(B)
2.5 V V
ref(A)
and 5 V V
ref(B)
3.3 V V
ref(A)
and 5 V V
ref(B)
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
Low 3.5
ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP20, DHVQFN20, TSSOP24, DHVQFN24, HVQFN24
3. Ordering information
Table 1.
Ordering information
Topside
mark
NVT2008
Number Package
of bits
Name
8
Description
Version
SOT764-1
Type number
NVT2008BQ
[1]
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
NVT2008PW
[1]
NVT2010BQ
[2]
NVT2008
NVT2010
8
10
SOT360-1
SOT815-1
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
HVQFN24
TSSOP24
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
4
0.85 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
NVT2010BS
[2]
NVT2010PW
[2]
N010
NVT2010
10
10
SOT616-1
SOT355-1
[1]
[2]
GTL2003 = NVT2008.
GTL2010 = NVT2010.
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
NVT2008BQ,115
NVT2008PW,118
NVT2010BQ,118
NVT2010BS,115
NVT2010BS,118
NVT2010PW
NVT2010PW,118
Package
DHVQFN20
TSSOP20
DHVQFN24
HVQFN24
HVQFN24
TSSOP24
Packing method
Reel 7” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 7” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Minimum
order quantity
3000
2500
3000
1500
6000
2500
Temperature
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
NVT2008BQ
NVT2008PW
NVT2010BQ
NVT2010BS
NVT2008_NVT2010
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 27 January 2014
2 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
4. Functional diagram
VREFA
VREFB
NVT20xx
EN
A1
SW
B1
An
SW
Bn
GND
002aae132
Fig 1.
Logic diagram of NVT2008/10 (positive logic)
5. Pinning information
5.1 Pinning
5.1.1 8-bit in TSSOP20 and DHVQFN20 packages
GND
2
3
4
5
1
20 EN
19 VREFB
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
B8 11
terminal 1
index area
VREFA
GND
VREFA
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 EN
19 VREFB
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
002aae225
A1
A2
A3
A4
A5
A6
A7
NVT2008BQ
6
7
8
9
A8 10
NVT2008PW
A8 10
002aae226
Transparent top view
Fig 2.
Pin configuration for TSSOP20
Fig 3.
Pin configuration for DHVQFN20
NVT2008_NVT2010
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 27 January 2014
3 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
5.1.2 10-bit in TSSOP24, DHVQFN24 and HVQFN24 packages
GND
VREFA
GND
VREFA
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
24 EN
23 VREFB
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
002aae227
2
3
4
5
6
7
8
9
24 EN
23 VREFB
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
B10 13
terminal 1
index area
A1
A2
A3
A4
A5
A6
A7
NVT2010BQ
NVT2010PW
A8 10
A9 11
A10 12
A8 10
A9 11
A10 12
1
002aae228
Transparent top view
Fig 4.
Pin configuration for TSSOP24
23 VREFA
Fig 5.
20 VREFB
Pin configuration for DHVQFN24
22 GND
24 A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
B10 10
B9 11
B8 12
7
8
9
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
002aae229
terminal 1
index area
NVT2010BS
Transparent top view
Fig 6.
Pin configuration for HVQFN24
NVT2008_NVT2010
All information provided in this document is subject to legal disclaimers.
A10
A8
A9
21 EN
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 27 January 2014
4 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
NVT2008BQ,
NVT2010BQ,
NVT2010BS
[2]
[1]
NVT2010PW
[2]
NVT2008PW
GND
VREFA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
VREFB
EN
1
2
3
4
5
6
7
8
9
10
-
-
18
17
16
15
14
13
12
11
-
-
19
20
1
2
3
4
5
6
7
8
9
10
11
12
22
21
20
19
18
17
16
15
14
13
23
24
22
23
24
1
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
11
10
20
21
high-voltage side reference
supply voltage for Bn
switch enable input; connect to
VREFB and pull-up through a
high resistor
high-voltage side; connect to
VREFB through a pull-up resistor
ground (0 V)
low-voltage side reference supply
voltage for An
low-voltage side; connect to
VREFA through a pull-up resistor
Description
[1]
[2]
8-bit NVT2008 available in TSSOP20, DHVQFN20 packages.
10-bit NVT2010 available in TSSOP24, DHVQFN24, HVQFN24 packages.
NVT2008_NVT2010
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 27 January 2014
5 of 33
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