PL903xxx
Revision 1.0
General Description
The PL903xxx series is a small form factor, high
performance OTP-base device and a member of Micrel’s
JitterBlocker, factory programmable jitter attenuators. The
JitterBlocker product family cleans deterministic jitter by
attenuating spurious components in the phase noise,
thereby improving the phase jitter and the overall phase
noise. The PL903xxx is capable of reducing multiple pico
seconds of phase jitter in a clock to a level below 1ps
RMS
,
making that clock usable for many more applications.
The PL903xxx operates on a single 2.5V or 3.3V supply
and is housed in a small QFN package for a broad range
of applications.
Input clock frequencies up to 200MHz can be filtered and
frequency translation allows for output clock frequencies
up to 840MHz.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
•
•
•
•
Lowest-power, smallest programmable jitter attenuator
Input frequency up to 200MHz
Output frequency up to 840MHz
Jitter attenuation 20dB at 3MHz spur frequency
Additive phase jitter or phase jitter floor:
−
55fs for 1.875MHz to 20MHz
−
251fs for 12kHz to 20MHz
Single ended CMOS input
One differential or two single ended outputs. Output
logic types supported are LVPECL, LVDS, HCSL and
LVCMOS (single ended or differential).
Operating temperature range from –40°C to +85°C
Available in 24-pin QFN RoHS-compliant package.
Related devices:
−
PL902xxx: LVCMOS, period jitter cleaning.
−
PL904xxx: Differential input, two differential outputs,
phase noise cleaning
•
•
•
•
•
Block Diagram
•
•
•
•
•
•
•
Applications
1/10/40/100 Gigabit Ethernet (GbE)
SONET/SDH
PCI Express
CPRI/OBSAI wireless base stations
Fibre Channel
SAS/SATA
DIMM
Ripple Blocker is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
October 2, 2014
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL903xxx
Ordering Information
Part Number
PL903xxxUMG
PL903xxxUMG TR
Marking
PL903
XXX
PL903
XXX
Shipping
Tray
Tape and Reel
Ambient Temp. Range
–40° to +85°C
–40° to +85°C
Package
QFN-24L
QFN-24L
Pin Configuration
24-Pin QFN
Pin Description
Pin Number
22
23
Pin Name
Q
/Q
Pin Type
O
Pin Level
Various
Pin Function
Clock output.
(1)
Can be programmed to one of the following logic types:
LVPECL, LVDS, HCSL, or LVCMOS.
Reference clock input.
Can be programmed to either LVCMOS levels or smaller
amplitude signals from other logic types.
Output enable control input with pull-up (45kΩ).
Core power supply.
Output buffer power supply.
Power supply ground.
Used for production test
Do not connect anything to these pins.
Not internally connected. No need to connect anything to
these pins.
GND
The center pad must be connected to the ground plane
both for electrical ground and thermal relief.
3
12
1, 20
17, 24
2, 8, 13, 14
15, 21
4, 5, 7, 9, 11
16, 18
6, 10, 19
ePad
Note:
REFIN
OE
VDD
VDDO
VSS
TEST
NC
Exposed Pad
I, (SE)
I
PWR
PWR
PWR
Various
LVCMOS
1. In case of LVCMOS, the output pair can provide two single-ended LVCMOS outputs.
October 2, 2014
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Revision 1.0
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or (408) 955-1690
Micrel, Inc.
PL903xxx
Functional Description
PL903xxx series is a very flexible, advanced programmable jitter filter design for high performance, small form-factor
applications. The PL903xxx accepts a reference clock input between 12MHz and 200MHz and is capable of producing
one differential output up to 840MHz or two single ended outputs up to 250MHz. The most common configuration will be
with the same input and output frequency but this flexible design also allows frequency translation from one frequency to
another frequency, as long as both frequencies are within the specified ranges for input and output.
Jitter Attenuation
Typically the jitter attenuation settings will be optimized for
one particular input and output frequency. Customization
of attenuation properties is possible.
The lowest possible output phase jitter, or phase jitter
floor, is 251fs for the 12kHz to 20MHz integration range
and 55fs for the Gigabit Ethernet integration range of
1.875MHz to 20MHz. The PL903xxx excels at attenuating
deterministic jitter that presents itself as spurs in the phase
noise plot above 1MHz.
Clock Output
The output pins Q and /Q make a differential output that
can be programmed to several different logic types:
LVPECL, LVDS, HCSL or LVCMOS. In the case of
LVCMOS, there are three possible configurations:
1. One single-ended output with the complementary pin
disabled to a high impedance.
2. Two single-ended, in-phase outputs.
3. A differential output with opposite phases at the two
output pins
Output Frequency
The most common configuration is where the output
frequency is the same as the input frequency. However,
frequency translations are possible. The input frequency
upper limit is 200MHz, but the output can go up to
840MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable and
disable the clock output(s) by toggling the OE pin. The OE
pin incorporates a 45kΩ pull-up resistor giving a default
condition of logic “1” that enables the output(s).
Reference (Noisy) Clock Input (REFIN)
The input requires a single-ended CMOS signal. The
frequency range for the input is 12MHz to 200MHz.
October 2, 2014
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Revision 1.0
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or (408) 955-1690
Micrel, Inc.
PL903xxx
Absolute Maximum Ratings
(2)
Supply Voltage (V
DD
, V
DDO
) ......................................... +4.6V
Input Voltage (V
IN
) ................................
−0.5V
to V
DD
+ 0.5V
Lead Temperature (soldering, 20s) ............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts)......................... –65°C to +150°C
Operating Ratings
(3)
Supply Voltage (V
DD
, V
DDO
) .................. +2.375V to +3.465V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
(4)
Junction Thermal Resistance
(θ
JA
), Still-Air ...................................................... 50°C/W
DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C.
Symbol
V
DD
Parameter
Power supply voltage
LVPECL, 312.5MHz
Outputs open
I
DD
Total supply current, V
DD
+ V
DDO
HCSL (PCIe), 100MHz
Outputs terminated with 50Ω to V
SS
2 × LVCMOS, 125MHz
Outputs open
Condition
Min.
2.375
100
80
70
Typ.
Max.
3.465
120
100
90
Units
V
mA
mA
mA
LVCMOS Inputs (OE, REFIN) DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C.
Symbol
V
IH
V
IN
I
IH
I
IL
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. The device is not guaranteed to function outside its operating ratings.
4. Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
5. The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables after thermal equilibrium has been
established.
Parameter
Input high voltage
Input low voltage
Input high current
Input low current
Condition
Min.
70% V
DD
V
SS
– 0.3
Typ.
Max.
V
DD
+
0.3
30%
V
DD
150
Units
V
V
µA
µA
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
–150
October 2, 2014
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PL903xxx
LVDS Output DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 100Ω across Q and /Q.
Symbol
V
OD
ΔV
OD
V
OS
ΔV
OS
Parameter
Differential output voltage
V
OD
magnitude change
Offset voltage
V
OS
magnitude change
1.15
1.25
Condition
Figure 6
Min.
275
Typ.
350
Max.
475
40
1.50
50
Units
mV
mV
V
mV
HCSL Output DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 50Ω to V
SS
Symbol
V
OH
V
OL
V
SWING
Parameter
Output high voltage
Output low voltage
Output voltage swing
Condition
Figure 1, Figure 5
Figure 1, Figure 5
Figure 1, Figure 5
Min.
660
−150
630
Typ.
700
0
700
Max.
850
27
1000
Units
mV
mV
mV
LVPECL Output DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 50Ω to V
DD
−
2V
Symbol
V
OH
V
OL
V
SWING
Parameter
Output high voltage
Output low voltage
Output voltage swing
Condition
Figure 1, Figure 4
Figure 1, Figure 4
Figure 1, Figure 4
Min.
V
DD
– 1.145
V
DD
– 1.945
0.6
Typ.
V
DD
– 0.97
V
DD
– 1.77
0.8
Max.
V
DD
– 0.845
V
DD
– 1.645
1.0
Units
V
V
V
LVCMOS Output DC Electrical Characteristics
(5)
V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%; T
A
= –40°C to +85°C, R
L
= 50Ω to V
DD
/2
Symbol
V
OH
V
OL
Parameter
Output high voltage
Output low voltage
Condition
Figure 1, Figure 7
Figure 1, Figure 7
Min.
V
DD
– 0.7
0.6
Typ.
Max.
Units
V
V
October 2, 2014
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Revision 1.0
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or (408) 955-1690
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