74LVC1G80
Single D-type flip-flop; positive-edge trigger
Rev. 08 — 29 August 2007
Product data sheet
1. General description
The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
s
Wide supply voltage range from 1.65 V to 5.5 V
s
High noise immunity
s
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
s
±24
mA output drive (V
CC
= 3.0 V)
s
CMOS low power consumption
s
Latch-up performance exceeds 250 mA
s
Direct interface with TTL levels
s
Inputs accept voltages up to 5 V
s
Multiple package options
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +125
°C
NXP Semiconductors
74LVC1G80
Single D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G80GW
74LVC1G80GV
74LVC1G80GM
74LVC1G80GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP5
SC-74A
XSON6
XSON6
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1
×
0.5 mm
Version
SOT353-1
SOT753
SOT886
SOT891
Type number
4. Marking
Table 2.
Marking codes
Marking
VT
V80
VT
VT
Type number
74LVC1G80GW
74LVC1G80GV
74LVC1G80GM
74LVC1G80GF
5. Functional diagram
1
D
Q
4
1
2
CP
mna649
D
CP
001aac523
4
2
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC1G80_8
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 08 — 29 August 2007
2 of 16
NXP Semiconductors
74LVC1G80
Single D-type flip-flop; positive-edge trigger
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
mna651
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G80
74LVC1G80
D
CP
1
2
GND
GND
3
001aab662
D
5
V
CC
1
6
V
CC
D
CP
74LVC1G80
1
2
3
6
5
4
V
CC
n.c.
Q
CP
2
5
n.c.
3
4
Q
GND
4
Q
001aab663
001aaf535
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT353-1
and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
D
CP
GND
Q
n.c.
V
CC
Pin description
Pin
SOT353-1/SOT753
1
2
3
4
-
5
SOT886/SOT891
1
2
3
4
5
6
data input
data pulse input
ground (0 V)
data output
not connected
supply voltage
Description
74LVC1G80_8
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 08 — 29 August 2007
3 of 16
NXP Semiconductors
74LVC1G80
Single D-type flip-flop; positive-edge trigger
7. Functional description
Table 4.
Input
CP
↑
↑
L
[1]
Function table
[1]
Output
D
L
H
X
Q
H
L
q
H = HIGH voltage level;
L = LOW voltage level.
↑
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
+6.5
±50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
°C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
−0.5
−0.5
-
-
−100
T
amb
=
−40 °C
to +125
°C
[3]
-
−65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP5 and SC-74A packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
74LVC1G80_8
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 08 — 29 August 2007
4 of 16
NXP Semiconductors
74LVC1G80
Single D-type flip-flop; positive-edge trigger
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
V
CC
= 0 V; Power-down mode
Conditions
Min
1.65
0
0
0
−40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
−40 °C
to +85
°C
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 5.5 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−24
mA; V
CC
= 3.0 V
I
O
=
−32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
input leakage current
power-off leakage current
V
I
= 5.5 V or GND; V
CC
= 0 V to 5.5 V
V
CC
= 0 V; V
I
or V
O
= 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
0.1
0.45
0.3
0.4
0.55
0.55
±5
±10
V
V
V
V
V
V
µA
µA
V
CC
−
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.65
×
V
CC
1.7
2.0
0.7
×
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
V
V
V
V
V
V
V
V
Conditions
Min
Typ
[1]
Max
Unit
74LVC1G80_8
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 08 — 29 August 2007
5 of 16
stm32/stm8
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