74F112 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised September 2000
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on S
D
or C
D
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on S
D
and C
D
force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q
and Q HIGH
Ordering Code:
Order Number
74F112SC
74F112SJ
74F112PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009472
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74F112
Unit Loading/Fan Out
U.L.
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Description
1.0/1.0
1.0/4.0
1.0/5.0
1.0/5.0
50/33.3
Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
2.4 mA
20
µ
A/
−
3.0 mA
20
µ
A/
−
3.0 mA
Q
1
, Q
2
, Q
1
, Q
2
Outputs
−
1 mA/20 mA
Truth Table
Inputs
S
D
L
H
L
H
H
H
H
C
D
H
L
L
H
H
H
H
CP
X
X
J
X
X
X
h
l
h
l
K
X
X
X
h
h
l
l
Outputs
Q
H
L
H
Q
0
L
H
Q
0
Q
L
H
H
Q
0
H
L
Q
0
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Clock Transition
Q
0
(Q
0
)
=
Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
X
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F112
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
4.75
3.75
−0.6
−2.4
−3.0
I
OS
I
CCH
I
CCL
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
12
12
−150
19
19
mA
mA
mA
Max
Max
Max
mA
Max
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
Min
Max
Max
Max
0.0
0.0
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All other pins grounded
V
IOD
=
150 mV
All other pins grounded
V
IN
=
0.5V (J
n
, K
n
)
V
IN
=
0.5V (CP
n
)
V
IN
=
0.5V (C
Dn
, S
Dn
)
V
OUT
=
0V
V
O
=
HIGH
V
O
=
LOW
3
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74F112
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
, S
Dn
to Q
n
, Q
n
85
2.0
2.0
2.0
2.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
105
5.0
5.0
4.5
4.5
6.5
6.5
6.5
6.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
80
2.0
2.0
2.0
2.0
7.5
7.5
7.5
7.5
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
J
n
or K
n
to CP
n
Hold Time, HIGH or LOW
J
n
or K
n
to CP
n
CP Pulse Width
HIGH or LOW
Pulse Width, LOW
C
Dn
or S
Dn
Recovery Time
S
Dn
, C
Dn
to CP
4.0
3.0
0
0
4.5
4.5
4.5
4.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
5.0
3.5
0
0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Max
Units
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4
74F112
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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