• Protocol Support - Single I/O, Dual I/O and Quad I/O
• Support DTR (Double Transfer Rate) Mode
• Support clock frequency up to 133MHz
MX25L12845G
Contents
1. FEATURES .............................................................................................................................................................. 5
2. GENERAL DESCRIPTION ..................................................................................................................................... 6
6. DATA PROTECTION................................................................................................................................................ 9
Table 2. Protected Area Sizes ...................................................................................................................10
Table 7. Status Register ............................................................................................................................32
4 x I/O Read Mode (4READ) ................................................................................................................... 45
4 x I/O Double Transfer Rate Read Mode (4DTRD) ................................................................................ 47
Preamble Bit ........................................................................................................................................... 49
9-36. Program Suspend .................................................................................................................................... 77
11. POWER-ON STATE ............................................................................................................................................. 96
14. ERASE AND PROGRAMMING PERFORMANCE ............................................................................................ 105
15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ................................................................ 105
16. DATA RETENTION ............................................................................................................................................ 106
18. ORDERING INFORMATION .............................................................................................................................. 107
19. PART NAME DESCRIPTION ............................................................................................................................. 108
20. PACKAGE INFORMATION ................................................................................................................................ 109
21. REVISION HISTORY ......................................................................................................................................... 115
P/N: PM2145
4
Rev. 1.6, October 05, 2017
MX25L12845G
3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
•
134,217,728 x 1 bit structure
or 67,108,864 x 2 bits (two I/O mode) structure
or 33,554,432 x 4 bits (four I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
• Fast read for SPI mode
- Support clock frequency up to 133MHz for all
protocols
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Configurable dummy cycle number for fast read
operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks
with 32K byte each or Equal Blocks with 64K byte
each
- Any Block can be erased individually
• Programming:
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of
the area to be protected against program and erase
instructions
- Individual sector protection function (Solid Protect)
• Additional 4K bit security OTP
-
Features unique identifier
-
Factory locked identifiable, and customer lockable
•
•
•
Command Reset
Program/Erase Suspend and Resume operation
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device
ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
Support Serial Flash Discoverable Parameters
(SFDP) mode
•
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2
x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for
2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware Write Protection or Serial Data Input/
Output for 4 x I/O read mode
• RESET#/SIO3
- Hardware Reset pin or Serial Data Input/Output for